(no commit message)

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 0b3c06ef074e5086e3d9d593d4f0cc6e66e3c4e0..8549265529d73501915b495a6e821fe4cc59557e 100644 (file)
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -50,5 +50,10 @@ JIT Translation or Illegal Instruction traps.  SVSTATE joins MSR and PC
 as direct peers and must be switched on any context-switch (Trap or
 Exception)
 
+* PC is saved/restored to/from SRR0
+* MSR is saved/restored to/from SRR1
+* SVSTATE **must** also be saved/restored to/from SVSRR1
 
-* MSR is saved/restored to SRR1
+Any implementation that implements Hypervisor Mode must also
+correspondingly follow the Power ISA Spec for HSRR0 and HSRR1,
+and must save/restore SVSTATE to/from HSVSRR1.