remove src suboffset

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index ce705743ba9ba0f1109fe5d85f68fa26f9540b55..213cd2a888107c7030decc79e73e59a6497734a4 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -30,7 +30,6 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #define SRC_PREDINT 1
 #define PRED_ARGS dest_pred,dest_pred,dest_pred,dest_pred,dest_pred,&dest_pred
 #define OFFS_ARGS dest_offs,dest_offs,dest_offs,dest_offs,dest_offs,dest_offs
-#define SUBO_ARGS dest_subo,dest_subo,dest_subo,dest_subo,dest_subo,dest_subo
 #else
 #define sv_enabled true
 #endif
@@ -58,14 +57,13 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t dest_pred = ~0x0;
   bool dest_pset = false;
   int *dest_offs = &(p->get_state()->sv().destoffs);
-  int *dest_subo = &(p->get_state()->sv().dsvoffs);
+  int *suboffs = &(p->get_state()->sv().dsvoffs);
   bool zeroing = false;
 #ifdef INSN_CATEGORY_TWINPREDICATION
   reg_t src_preg = 0;
   reg_t src_pred = ~0x0;
   bool src_pset = false;
   int *src_offs = &(p->get_state()->sv().srcoffs);
-  int *src_subo = &(p->get_state()->sv().ssvoffs);
   bool zeroingsrc = false;
 #endif
 #ifdef INSN_TYPE_BRANCH
@@ -75,7 +73,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
   sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen,
                  INSN_SRC_FLEN, INSN_DEST_FLEN,
-                 PRED_ARGS, OFFS_ARGS, SUBO_ARGS,
+                 PRED_ARGS, OFFS_ARGS, suboffs,
 #ifdef INSN_TYPE_SIGNED
                  true
 #else
@@ -104,10 +102,10 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
             s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
             vlen, subvl);
 #ifdef INSN_TYPE_C_STACK_LD
-    sp = insn._remap(X_SP, true, src_offs, src_subo);
+    sp = insn._remap(X_SP, true, src_offs, suboffs);
 #endif
 #ifdef INSN_TYPE_C_STACK_ST
-    sp = insn._remap(X_SP, true, dest_offs, dest_subo);
+    sp = insn._remap(X_SP, true, dest_offs, suboffs);
 #endif
 #ifdef INSN_TYPE_BRANCH
     // all branch ops are rs1, rs2.  take target (dest) predicate from rs2.
@@ -178,7 +176,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
         fprintf(stderr, "pre twin reg %s src %d dest %d pred %lx %lx\n",
             xstr(INSN), *src_offs, *dest_offs, src_pred, dest_pred);
 #endif
-    if (inc_offs(vlen, subvl, *dest_subo))
+    if (inc_offs(vlen, subvl, *suboffs))
     {
       if (!zeroingsrc)
       {
@@ -290,7 +288,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
       {
         break;
       }
-      if (inc_offs(vlen, subvl, *dest_subo)) {
+      if (inc_offs(vlen, subvl, *suboffs)) {
 #ifdef INSN_CATEGORY_TWINPREDICATION
           (*src_offs) += 1;
 #endif

diff --git a/riscv/sv.cc b/riscv/sv.cc
index e5da9f34a9093a9ceaed2f230d7aad2d8c4644ba..24a7f02ae2b970df58a06df03e8ce7761e2f50aa 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -44,8 +44,7 @@ sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
             int *o_imm,
-            int *s_rd, int *s_rs1, int *s_rs2, int *s_rs3, int *s_sp,
-            int *s_imm,
+            int *s_offs,
             bool _sign) :
             insn_t(bits), p(pr), src_bitwidth(0),
             xlen(_xlen), src_flen(_src_flen), dest_flen(_dest_flen),
@@ -55,9 +54,7 @@ sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
             offs_sp(o_sp),
             offs_imm(o_imm),
-            subo_rd(s_rd), subo_rs1(s_rs1), subo_rs2(s_rs2), subo_rs3(s_rs3),
-            subo_sp(s_sp),
-            subo_imm(s_imm),
+            suboffs(s_offs), 
             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp),
             save_branch_addr(0)
 {

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 060aa3af841fc93915c04ccff80eab0bce0e34af..a28d5ce249251b17221760752b1befef8f4a1c74 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -44,8 +44,7 @@ public:
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
             int *o_imm,
-            int *s_rd, int *s_rs1, int *s_rs2, int *s_rs3, int *s_sp,
-            int *s_imm,
+            int *s_offs,
             bool _sign);
 
   uint8_t reg_elwidth(reg_t reg, bool intreg);
@@ -75,29 +74,29 @@ public:
                      { return predicated(_rvc_sp  (use_offs), psp ); }
 
   reg_spec_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD,
-                                    offs_rd, subo_rd); }
+                                    offs_rd, suboffs); }
   reg_spec_t _rs1() { return _remap(insn_t::rs1(), fimap & REG_RS1,
-                                    offs_rs1, subo_rs1); }
+                                    offs_rs1, suboffs); }
   reg_spec_t _rs2() { return _remap(insn_t::rs2(), fimap & REG_RS2,
-                                    offs_rs2, subo_rs2); }
+                                    offs_rs2, suboffs); }
   reg_spec_t _rs3() { return _remap(insn_t::rs3(), fimap & REG_RS3,
-                                    offs_rs3, subo_rs3); }
+                                    offs_rs3, suboffs); }
   reg_spec_t _rvc_rs1 () { return _remap(insn_t::rvc_rs1(),
                                     fimap & REG_RVC_RS1,
-                                    offs_rs1, subo_rs1); }
+                                    offs_rs1, suboffs); }
   reg_spec_t _rvc_rs1s() { return _remap(insn_t::rvc_rs1s(),
                                     fimap & REG_RVC_RS1S,
-                                    offs_rs1, subo_rs1); }
+                                    offs_rs1, suboffs); }
   reg_spec_t _rvc_rs2 () { return _remap(insn_t::rvc_rs2(),
                                     fimap & REG_RVC_RS2,
-                                    offs_rs2, subo_rs2); }
+                                    offs_rs2, suboffs); }
   reg_spec_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(),
                                     fimap & REG_RVC_RS2S,
-                                    offs_rs2, subo_rs2); }
+                                    offs_rs2, suboffs); }
   reg_spec_t _rvc_sp  (bool use_offs=true)
                 { return _remap(2, true, // sp always 2, always int
                                 use_offs ? offs_sp : NULL,
-                                use_offs ? subo_sp : NULL); }
+                                use_offs ? suboffs : NULL); }
 
   void setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs,
              reg_t *target_reg, bool zeroing, bool inv);
@@ -139,7 +138,7 @@ public:
   uint64_t get_if_one_reg_vectorised() { return at_least_one_reg_vectorised; }
 
   int *get_sp_offs() { return offs_sp; }
-  int *get_sp_subo() { return subo_sp; }
+  int *get_sp_subo() { return suboffs; }
 
 private:
   bool vloop_continue;
@@ -152,12 +151,7 @@ private:
   int *offs_sp;
   int *offs_imm;
 
-  int *subo_rd;
-  int *subo_rs1;
-  int *subo_rs2;
-  int *subo_rs3;
-  int *subo_sp;
-  int *subo_imm;
+  int *suboffs;
 
   uint64_t &prd;
   uint64_t &prs1;