DSP48E1 sim model: add SIMD tests

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index b738d97126071014ba3555efb4006c558f2e747e..8b6eaae5d3378e2b6627cbc7edfff9dea049bf82 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -468,7 +468,7 @@ module DSP48E1 (
         if (SEL_MASK != "MASK")     $fatal(1, "Unsupported SEL_MASK value");
         if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
         if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value");
-        if (USE_SIMD != "ONE48")    $fatal(1, "Unsupported USE_SIMD value");
+        if (USE_SIMD != "ONE48" && USE_SIMD != "TWO24" && USE_SIMD != "FOUR12")    $fatal(1, "Unsupported USE_SIMD value");
         if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value");
         if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value");
         if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value");

diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh
index 337530e87253b201e41489eb557fae8e5d8d1e1e..2acd97eb47d1c7326d807bb9ebdccffe83492691 100644 (file)
--- a/techlibs/xilinx/tests/test_dsp_model.sh
+++ b/techlibs/xilinx/tests/test_dsp_model.sh
@@ -4,8 +4,10 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v >
 if [ ! -f "test_dsp_model_ref.v" ]; then
        cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
 fi
-for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc  \
-       mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc
+for tb in simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
+    mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc  \
+       mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc \
+       
 do
        iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
        vvp -N ./test_dsp_model

diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v
index 7086634d223762f8396173bbd178acf08e3511a2..04d5b26ab5b7a30d047e6761ced42f379a119a28 100644 (file)
--- a/techlibs/xilinx/tests/test_dsp_model.v
+++ b/techlibs/xilinx/tests/test_dsp_model.v
@@ -92,6 +92,8 @@ module testbench;
                        if (AREG != 2 && INMODE[0]) config_valid = 0;
                        if (BREG != 2 && INMODE[4]) config_valid = 0;
 
+                       if (USE_SIMD != "ONE48" && OPMODE[3:0] == 4'b0101) config_valid = 0;
+
                        if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
                        if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
                        if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0;
@@ -486,4 +488,110 @@ module mult_allreg_preadd_nocasc;
                .IS_INMODE_INVERTED (5'b0),
                .IS_OPMODE_INVERTED (7'b0)
        ) testbench ();
+endmodule
+
+module mult_inreg_preadd_nocasc;
+       testbench #(
+               .ACASCREG           (1),
+               .ADREG              (0),
+               .ALUMODEREG         (0),
+               .AREG               (1),
+               .AUTORESET_PATDET   ("NO_RESET"),
+               .A_INPUT            ("DIRECT"),
+               .BCASCREG           (1),
+               .BREG               (1),
+               .B_INPUT            ("DIRECT"),
+               .CARRYINREG         (0),
+               .CARRYINSELREG      (0),
+               .CREG               (1),
+               .DREG               (1),
+               .INMODEREG          (0),
+               .MREG               (0),
+               .OPMODEREG          (0),
+               .PREG               (0),
+               .SEL_MASK           ("MASK"),
+               .SEL_PATTERN        ("PATTERN"),
+               .USE_DPORT          ("TRUE"),
+               .USE_MULT           ("DYNAMIC"),
+               .USE_PATTERN_DETECT ("NO_PATDET"),
+               .USE_SIMD           ("ONE48"),
+               .MASK               (48'h3FFFFFFFFFFF),
+               .PATTERN            (48'h000000000000),
+               .IS_ALUMODE_INVERTED(4'b0),
+               .IS_CARRYIN_INVERTED(1'b0),
+               .IS_CLK_INVERTED    (1'b0),
+               .IS_INMODE_INVERTED (5'b0),
+               .IS_OPMODE_INVERTED (7'b0)
+       ) testbench ();
+endmodule
+
+module simd12_preadd_noreg_nocasc;
+       testbench #(
+               .ACASCREG           (0),
+               .ADREG              (0),
+               .ALUMODEREG         (0),
+               .AREG               (0),
+               .AUTORESET_PATDET   ("NO_RESET"),
+               .A_INPUT            ("DIRECT"),
+               .BCASCREG           (0),
+               .BREG               (0),
+               .B_INPUT            ("DIRECT"),
+               .CARRYINREG         (0),
+               .CARRYINSELREG      (0),
+               .CREG               (0),
+               .DREG               (0),
+               .INMODEREG          (0),
+               .MREG               (0),
+               .OPMODEREG          (0),
+               .PREG               (0),
+               .SEL_MASK           ("MASK"),
+               .SEL_PATTERN        ("PATTERN"),
+               .USE_DPORT          ("TRUE"),
+               .USE_MULT           ("DYNAMIC"),
+               .USE_PATTERN_DETECT ("NO_PATDET"),
+               .USE_SIMD           ("FOUR12"),
+               .MASK               (48'h3FFFFFFFFFFF),
+               .PATTERN            (48'h000000000000),
+               .IS_ALUMODE_INVERTED(4'b0),
+               .IS_CARRYIN_INVERTED(1'b0),
+               .IS_CLK_INVERTED    (1'b0),
+               .IS_INMODE_INVERTED (5'b0),
+               .IS_OPMODE_INVERTED (7'b0)
+       ) testbench ();
+endmodule
+
+
+module simd24_preadd_noreg_nocasc;
+       testbench #(
+               .ACASCREG           (0),
+               .ADREG              (0),
+               .ALUMODEREG         (0),
+               .AREG               (0),
+               .AUTORESET_PATDET   ("NO_RESET"),
+               .A_INPUT            ("DIRECT"),
+               .BCASCREG           (0),
+               .BREG               (0),
+               .B_INPUT            ("DIRECT"),
+               .CARRYINREG         (0),
+               .CARRYINSELREG      (0),
+               .CREG               (0),
+               .DREG               (0),
+               .INMODEREG          (0),
+               .MREG               (0),
+               .OPMODEREG          (0),
+               .PREG               (0),
+               .SEL_MASK           ("MASK"),
+               .SEL_PATTERN        ("PATTERN"),
+               .USE_DPORT          ("TRUE"),
+               .USE_MULT           ("DYNAMIC"),
+               .USE_PATTERN_DETECT ("NO_PATDET"),
+               .USE_SIMD           ("TWO24"),
+               .MASK               (48'h3FFFFFFFFFFF),
+               .PATTERN            (48'h000000000000),
+               .IS_ALUMODE_INVERTED(4'b0),
+               .IS_CARRYIN_INVERTED(1'b0),
+               .IS_CLK_INVERTED    (1'b0),
+               .IS_INMODE_INVERTED (5'b0),
+               .IS_OPMODE_INVERTED (7'b0)
+       ) testbench ();
 endmodule
\ No newline at end of file