vendor.xilinx_*: Set IOB attribute on cels instead of nets.

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index a5f6bd657f0118cd1bca78ff08cb08e86590e469..899defc320fc7486019e0fc5e67dcb8b3cc3fbc6 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -175,19 +175,14 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         def get_dff(clk, d, q):
             # SDR I/O is performed by packing a flip-flop into the pad IOB.
             for bit in range(len(q)):
-                _q = Signal()
-                _q.attrs["IOB"] = "TRUE"
-                # Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing unless
-                # we prevent it from being optimized.
-                _q.attrs["DONT_TOUCH"] = "TRUE"
                 m.submodules += Instance("FDCE",
+                    a_IOB="TRUE",
                     i_C=clk,
                     i_CE=Const(1),
                     i_CLR=Const(0),
                     i_D=d[bit],
-                    o_Q=_q
+                    o_Q=q[bit]
                 )
-                m.d.comb += q[bit].eq(_q)
 
         def get_iddr(clk, d, q1, q2):
             for bit in range(len(q1)):

diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index a6158bb29e4ac1b8e6ab2e7590688f86620d8c64..a8e265a69a2d7a07a3d37aad8a31eea6f622136e 100644 (file)
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -212,16 +212,14 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         def get_dff(clk, d, q):
             # SDR I/O is performed by packing a flip-flop into the pad IOB.
             for bit in range(len(q)):
-                _q = Signal()
-                _q.attrs["IOB"] = "TRUE"
                 m.submodules += Instance("FDCE",
+                    a_IOB="TRUE",
                     i_C=clk,
                     i_CE=Const(1),
                     i_CLR=Const(0),
                     i_D=d[bit],
-                    o_Q=_q,
+                    o_Q=q[bit]
                 )
-                m.d.comb += q[bit].eq(_q)
 
         def get_iddr(clk, d, q0, q1):
             for bit in range(len(q0)):

diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 663ff2edcdc9502b42aead697298a71c282c76cd..15aadd4cc41750679769fdd180983e61d35a7fd6 100644 (file)
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -175,19 +175,14 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
         def get_dff(clk, d, q):
             # SDR I/O is performed by packing a flip-flop into the pad IOB.
             for bit in range(len(q)):
-                _q = Signal()
-                _q.attrs["IOB"] = "TRUE"
-                # Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing unless
-                # we prevent it from being optimized.
-                _q.attrs["DONT_TOUCH"] = "TRUE"
                 m.submodules += Instance("FDCE",
+                    a_IOB="TRUE",
                     i_C=clk,
                     i_CE=Const(1),
                     i_CLR=Const(0),
                     i_D=d[bit],
-                    o_Q=_q
+                    o_Q=q[bit]
                 )
-                m.d.comb += q[bit].eq(_q)
 
         def get_iddr(clk, d, q1, q2):
             for bit in range(len(q1)):