targets: use new prefered way to add wishbone slave

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 7b36a493a0bacd232793452ce5028752656f95fa..4e3a0a0799aba6e39d4b43829d19ebb8a4b52ecc 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -10,7 +10,6 @@ from migen import *
 from litex.boards.platforms import arty
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -85,7 +84,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index ac42607550f8b670bdb258e0171be25e0d735195..d025340ebdf3694c185ace9966b947382a4e7ea2 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -10,7 +10,6 @@ from migen import *
 from litex.boards.platforms import genesys2
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -78,7 +77,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 0a6205c3136f432ab7167098873850d3800fd9d8..4bb90216191890b2deee5bbeb0014dd7ba026216 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -12,7 +12,6 @@ from migen import *
 from litex.boards.platforms import kc705
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -80,7 +79,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index e6106aabd2d8062bda6960022eadbaf30393f82f..04670b82ba1a448340bfc6b9399913d4cd0d5f5e 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -10,7 +10,6 @@ from migen import *
 from litex.boards.platforms import kcu105
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -117,7 +116,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 2f98e0bcbbea698868b1438d491dee7c59f2949e..13d6975447b1a2894e01cc1179c7ce60ee0d7ce2 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -10,7 +10,6 @@ from migen import *
 from litex.boards.platforms import netv2
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -82,7 +81,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index d1c451ffc13ca8efc6cbe514b5cef9097be8691a..00f071166014b51ec0a7fe01e18499efe507200f 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -10,7 +10,6 @@ from migen import *
 from litex.boards.platforms import nexys4ddr
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -84,7 +83,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 39b235261d19b76f8497dce0c48d3f31e7406530..ad78f538f935a96f7914644a4fa1f04170042fbc 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -10,7 +10,6 @@ from migen import *
 from litex.boards.platforms import nexys_video
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -82,7 +81,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index f0af059e05ec7aedcf4f80a74d4eaef5e014c0a4..f8bcd948fee6cce1c233d26b6d5d83a0b48e235e 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -43,7 +43,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index b0a15ff38aaffb1fd0a2d81894dba4a06fcea889..9094992f0d1f5ef41fb8d221acca9a3ad71061ed 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -12,7 +12,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex.boards.platforms import versa_ecp5
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import mem_decoder
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -116,7 +115,7 @@ class EthernetSoC(BaseSoC):
         self.add_csr("ethphy")
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index b255d9173f449027d46fdf868bc213180eec10b8..b0238ce12e4133f161b0922322b55a5efdf5d0c1 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -17,7 +17,6 @@ from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 from litex.soc.cores import uart
-from litex.soc.integration.soc_core import mem_decoder
 
 from litedram.common import PhySettings
 from litedram.modules import MT48LC16M16
@@ -153,7 +152,7 @@ class SimSoC(SoCSDRAM):
             if with_etherbone:
                 ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx":  "ethphy_eth_rx"})(ethmac)
             self.submodules.ethmac = ethmac
-            self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+            self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
             self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
             self.add_csr("ethmac")
             self.add_interrupt("ethmac")