move generic modules to generic/__init__.py

diff --git a/liteeth/common.py b/liteeth/common.py
index 25562dc1c5519aa780654c7ed80f3ee3b3d11003..cea70727f992794b45073f5d754379f718ee08e0 100644 (file)
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -278,153 +278,3 @@ def eth_etherbone_mmap_description(dw):
                ("be", dw//8)
        ]
        return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-# Generic classes
-class Port:
-       def connect(self, port):
-               r = [
-                       Record.connect(self.source, port.sink),
-                       Record.connect(port.source, self.sink)
-               ]
-               return r
-
-# Generic modules
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class FlipFlop(Module):
-       def __init__(self, *args, **kwargs):
-               self.d = Signal(*args, **kwargs)
-               self.q = Signal(*args, **kwargs)
-               self.sync += self.q.eq(self.d)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Counter(Module):
-       def __init__(self, signal=None, **kwargs):
-               if signal is None:
-                       self.value = Signal(**kwargs)
-               else:
-                       self.value = signal
-               self.width = flen(self.value)
-               self.sync += self.value.eq(self.value+1)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Timeout(Module):
-       def __init__(self, length):
-               self.reached = Signal()
-               ###
-               value = Signal(max=length)
-               self.sync += If(~self.reached, value.eq(value+1))
-               self.comb += self.reached.eq(value == (length-1))
-
-class BufferizeEndpoints(ModuleDecorator):
-       def __init__(self, submodule, *args):
-               ModuleDecorator.__init__(self, submodule)
-
-               endpoints = get_endpoints(submodule)
-               sinks = {}
-               sources = {}
-               for name, endpoint in endpoints.items():
-                       if name in args or len(args) == 0:
-                               if isinstance(endpoint, Sink):
-                                       sinks.update({name : endpoint})
-                               elif isinstance(endpoint, Source):
-                                       sources.update({name : endpoint})
-
-               # add buffer on sinks
-               for name, sink in sinks.items():
-                       buf = Buffer(sink.description)
-                       self.submodules += buf
-                       setattr(self, name, buf.d)
-                       self.comb += Record.connect(buf.q, sink)
-
-               # add buffer on sources
-               for name, source in sources.items():
-                       buf = Buffer(source.description)
-                       self.submodules += buf
-                       self.comb += Record.connect(source, buf.d)
-                       setattr(self, name, buf.q)
-
-class EndpointPacketStatus(Module):
-       def __init__(self, endpoint):
-               self.start = Signal()
-               self.done = Signal()
-               self.ongoing = Signal()
-
-               ongoing = Signal()
-               self.comb += [
-                       self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
-                       self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
-               ]
-               self.sync += \
-                       If(self.start,
-                               ongoing.eq(1)
-                       ).Elif(self.done,
-                               ongoing.eq(0)
-                       )
-               self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
-
-class PacketBuffer(Module):
-       def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
-               self.sink = sink = Sink(description)
-               self.source = source = Source(description)
-
-               ###
-               sink_status = EndpointPacketStatus(self.sink)
-               source_status = EndpointPacketStatus(self.source)
-               self.submodules += sink_status, source_status
-
-               # store incoming packets
-               # cmds
-               def cmd_description():
-                       layout = [("error", 1)]
-                       return EndpointDescription(layout)
-               cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
-               self.submodules += cmd_fifo
-               self.comb += cmd_fifo.sink.stb.eq(sink_status.done)
-               if hasattr(sink, "error"):
-                       self.comb += cmd_fifo.sink.error.eq(sink.error)
-
-               # data
-               data_fifo = SyncFIFO(description, data_depth, buffered=True)
-               self.submodules += data_fifo
-               self.comb += [
-                       Record.connect(self.sink, data_fifo.sink),
-                       data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
-                       self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
-               ]
-
-               # output packets
-               self.fsm = fsm = FSM(reset_state="IDLE")
-               self.submodules += fsm
-               fsm.act("IDLE",
-                       If(cmd_fifo.source.stb,
-                               NextState("SEEK_SOP")
-                       )
-               )
-               fsm.act("SEEK_SOP",
-                       If(~data_fifo.source.sop,
-                               data_fifo.source.ack.eq(1)
-                       ).Else(
-                               NextState("OUTPUT")
-                       )
-               )
-               if hasattr(source, "error"):
-                       source_error = self.source.error
-               else:
-                       source_error = Signal()
-
-               fsm.act("OUTPUT",
-                       Record.connect(data_fifo.source, self.source),
-                       source_error.eq(cmd_fifo.source.error),
-                       If(source_status.done,
-                               cmd_fifo.source.ack.eq(1),
-                               NextState("IDLE")
-                       )
-               )
-
-               # compute almost full
-               if almost_full is not None:
-                       self.almost_full = Signal()
-                       self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
\ No newline at end of file

diff --git a/liteeth/core/__init__.py b/liteeth/core/__init__.py
index 6a143c9c682ab191525659f6e26a2b45d63c80c1..4d9b7147ac01fa538798ec225ffe67410a41516c 100644 (file)
--- a/liteeth/core/__init__.py
+++ b/liteeth/core/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac import LiteEthMAC
 from liteeth.core.arp import LiteEthARP
 from liteeth.core.ip import LiteEthIP

diff --git a/liteeth/core/arp/__init__.py b/liteeth/core/arp/__init__.py
index fbc31da0848cf8c91f258640ecd787fb31b5caf4..58b7aa894ef339ca0c03546cfbb926d39df687dd 100644 (file)
--- a/liteeth/core/arp/__init__.py
+++ b/liteeth/core/arp/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 

diff --git a/liteeth/core/etherbone/__init__.py b/liteeth/core/etherbone/__init__.py
index 8186193d33feb02ccbe81b0a23ef34bfb64a4d69..78f3d738cd5db6c441ec42b019b16761e7a3a743 100644 (file)
--- a/liteeth/core/etherbone/__init__.py
+++ b/liteeth/core/etherbone/__init__.py
@@ -1,8 +1,7 @@
 from liteeth.common import *
-
+from liteeth.generic import *
 from liteeth.generic.arbiter import Arbiter
 from liteeth.generic.dispatcher import Dispatcher
-
 from liteeth.core.etherbone.packet import *
 from liteeth.core.etherbone.probe import *
 from liteeth.core.etherbone.record import *

diff --git a/liteeth/core/etherbone/packet.py b/liteeth/core/etherbone/packet.py
index 1426db379e8047653a3bd5805ff9183f0eb09c69..22f72c5a57f19603cafe710fddcccdce2e45ebbd 100644 (file)
--- a/liteeth/core/etherbone/packet.py
+++ b/liteeth/core/etherbone/packet.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 

diff --git a/liteeth/core/etherbone/probe.py b/liteeth/core/etherbone/probe.py
index a447532cf3a237572b90744ffce8ae9e0275e98d..04eb9f6a2e45a5609ee6f09d694304b51312af32 100644 (file)
--- a/liteeth/core/etherbone/probe.py
+++ b/liteeth/core/etherbone/probe.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthEtherboneProbe(Module):
        def __init__(self):

diff --git a/liteeth/core/etherbone/record.py b/liteeth/core/etherbone/record.py
index 2ce525174091b4e556e563c6bf3586fd15e6825c..008be0027aa8062c994447abc961fe790d80f59a 100644 (file)
--- a/liteeth/core/etherbone/record.py
+++ b/liteeth/core/etherbone/record.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 

diff --git a/liteeth/core/etherbone/wishbone.py b/liteeth/core/etherbone/wishbone.py
index d49e43410f989106aba56c65f98faed980000699..2f5b17622062833433ae263c865bc25f51f88efa 100644 (file)
--- a/liteeth/core/etherbone/wishbone.py
+++ b/liteeth/core/etherbone/wishbone.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from migen.bus import wishbone
 
 class LiteEthEtherboneWishboneMaster(Module):

diff --git a/liteeth/core/icmp/__init__.py b/liteeth/core/icmp/__init__.py
index 35a69cc93dad6dcd602425c210235604bed47ece..79c519256348a34523378aa1ca9b7abad15c7ad4 100644 (file)
--- a/liteeth/core/icmp/__init__.py
+++ b/liteeth/core/icmp/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 

diff --git a/liteeth/core/ip/__init__.py b/liteeth/core/ip/__init__.py
index 00204aa49ba8b7d99da9a522b306b8789fef5774..17f854cbe5e17960c119e181747dc0e82c45b45c 100644 (file)
--- a/liteeth/core/ip/__init__.py
+++ b/liteeth/core/ip/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.core.ip.common import *
 
 class LiteEthIPTX(Module):

diff --git a/liteeth/core/ip/common.py b/liteeth/core/ip/common.py
index 17102767dbbf734a86735be59c5af7081b6344d0..8f27cdd5e9c5465e4d2d40e8202e0ae837b5436b 100644 (file)
--- a/liteeth/core/ip/common.py
+++ b/liteeth/core/ip/common.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 from liteeth.generic.crossbar import LiteEthCrossbar

diff --git a/liteeth/core/udp/__init__.py b/liteeth/core/udp/__init__.py
index 16ad1b8be0867e8563fd736dda3659baf4b79356..1bac7b72a1ace00bd45689405d36ad962d202f42 100644 (file)
--- a/liteeth/core/udp/__init__.py
+++ b/liteeth/core/udp/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.core.udp.common import *
 
 class LiteEthUDPTX(Module):

diff --git a/liteeth/core/udp/common.py b/liteeth/core/udp/common.py
index 187b829e441ff9945829efb7f59dc3bccbc295df..c5a2d472ce0c2c5936a330aa25325908a43bc609 100644 (file)
--- a/liteeth/core/udp/common.py
+++ b/liteeth/core/udp/common.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 from liteeth.generic.crossbar import LiteEthCrossbar

diff --git a/liteeth/generic/__init__.py b/liteeth/generic/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..643e98720d9d7fc7c1a02b0963327d675c124d78 100644 (file)
--- a/liteeth/generic/__init__.py
+++ b/liteeth/generic/__init__.py
@@ -0,0 +1,151 @@
+from liteeth.common import *
+
+# Generic classes
+class Port:
+       def connect(self, port):
+               r = [
+                       Record.connect(self.source, port.sink),
+                       Record.connect(port.source, self.sink)
+               ]
+               return r
+
+# Generic modules
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class FlipFlop(Module):
+       def __init__(self, *args, **kwargs):
+               self.d = Signal(*args, **kwargs)
+               self.q = Signal(*args, **kwargs)
+               self.sync += self.q.eq(self.d)
+
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class Counter(Module):
+       def __init__(self, signal=None, **kwargs):
+               if signal is None:
+                       self.value = Signal(**kwargs)
+               else:
+                       self.value = signal
+               self.width = flen(self.value)
+               self.sync += self.value.eq(self.value+1)
+
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class Timeout(Module):
+       def __init__(self, length):
+               self.reached = Signal()
+               ###
+               value = Signal(max=length)
+               self.sync += If(~self.reached, value.eq(value+1))
+               self.comb += self.reached.eq(value == (length-1))
+
+class BufferizeEndpoints(ModuleDecorator):
+       def __init__(self, submodule, *args):
+               ModuleDecorator.__init__(self, submodule)
+
+               endpoints = get_endpoints(submodule)
+               sinks = {}
+               sources = {}
+               for name, endpoint in endpoints.items():
+                       if name in args or len(args) == 0:
+                               if isinstance(endpoint, Sink):
+                                       sinks.update({name : endpoint})
+                               elif isinstance(endpoint, Source):
+                                       sources.update({name : endpoint})
+
+               # add buffer on sinks
+               for name, sink in sinks.items():
+                       buf = Buffer(sink.description)
+                       self.submodules += buf
+                       setattr(self, name, buf.d)
+                       self.comb += Record.connect(buf.q, sink)
+
+               # add buffer on sources
+               for name, source in sources.items():
+                       buf = Buffer(source.description)
+                       self.submodules += buf
+                       self.comb += Record.connect(source, buf.d)
+                       setattr(self, name, buf.q)
+
+class EndpointPacketStatus(Module):
+       def __init__(self, endpoint):
+               self.start = Signal()
+               self.done = Signal()
+               self.ongoing = Signal()
+
+               ongoing = Signal()
+               self.comb += [
+                       self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
+                       self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
+               ]
+               self.sync += \
+                       If(self.start,
+                               ongoing.eq(1)
+                       ).Elif(self.done,
+                               ongoing.eq(0)
+                       )
+               self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
+
+class PacketBuffer(Module):
+       def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
+               self.sink = sink = Sink(description)
+               self.source = source = Source(description)
+
+               ###
+               sink_status = EndpointPacketStatus(self.sink)
+               source_status = EndpointPacketStatus(self.source)
+               self.submodules += sink_status, source_status
+
+               # store incoming packets
+               # cmds
+               def cmd_description():
+                       layout = [("error", 1)]
+                       return EndpointDescription(layout)
+               cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
+               self.submodules += cmd_fifo
+               self.comb += cmd_fifo.sink.stb.eq(sink_status.done)
+               if hasattr(sink, "error"):
+                       self.comb += cmd_fifo.sink.error.eq(sink.error)
+
+               # data
+               data_fifo = SyncFIFO(description, data_depth, buffered=True)
+               self.submodules += data_fifo
+               self.comb += [
+                       Record.connect(self.sink, data_fifo.sink),
+                       data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
+                       self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
+               ]
+
+               # output packets
+               self.fsm = fsm = FSM(reset_state="IDLE")
+               self.submodules += fsm
+               fsm.act("IDLE",
+                       If(cmd_fifo.source.stb,
+                               NextState("SEEK_SOP")
+                       )
+               )
+               fsm.act("SEEK_SOP",
+                       If(~data_fifo.source.sop,
+                               data_fifo.source.ack.eq(1)
+                       ).Else(
+                               NextState("OUTPUT")
+                       )
+               )
+               if hasattr(source, "error"):
+                       source_error = self.source.error
+               else:
+                       source_error = Signal()
+
+               fsm.act("OUTPUT",
+                       Record.connect(data_fifo.source, self.source),
+                       source_error.eq(cmd_fifo.source.error),
+                       If(source_status.done,
+                               cmd_fifo.source.ack.eq(1),
+                               NextState("IDLE")
+                       )
+               )
+
+               # compute almost full
+               if almost_full is not None:
+                       self.almost_full = Signal()
+                       self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)

diff --git a/liteeth/generic/crossbar.py b/liteeth/generic/crossbar.py
index 4f8978567fd953e79c99b33894313839c01a31d4..b60da949469a5fa374183b21812cec7257884b25 100644 (file)
--- a/liteeth/generic/crossbar.py
+++ b/liteeth/generic/crossbar.py
@@ -1,6 +1,7 @@
 from collections import OrderedDict
 
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.arbiter import Arbiter
 from liteeth.generic.dispatcher import Dispatcher
 

diff --git a/liteeth/generic/depacketizer.py b/liteeth/generic/depacketizer.py
index fb1a1b3940860847f850850003e66b9978ecc03c..2d8ca86ca00a36f5fece9a599f3f6b2e4127032b 100644 (file)
--- a/liteeth/generic/depacketizer.py
+++ b/liteeth/generic/depacketizer.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 def _decode_header(h_dict, h_signal, obj):
        r = []

diff --git a/liteeth/generic/packetizer.py b/liteeth/generic/packetizer.py
index 627bb63d793dda9dd8c59de0de369107c3df3fd2..d15b8515b5117b238843401479288a8707297299 100644 (file)
--- a/liteeth/generic/packetizer.py
+++ b/liteeth/generic/packetizer.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 def _encode_header(h_dict, h_signal, obj):
        r = []

diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 2346584e402fde9e3a62761338f4f79060276255..5e88646bd1951de291c0351431a9d699166833fc 100644 (file)
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac.common import *
 from liteeth.mac.core import LiteEthMACCore
 from liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface

diff --git a/liteeth/mac/common.py b/liteeth/mac/common.py
index 128d8f17cf18a039ff424fffe6d9c07dca036e47..3a68c63212d7fa351a6be2f83beebd7b7427f0d4 100644 (file)
--- a/liteeth/mac/common.py
+++ b/liteeth/mac/common.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 from liteeth.generic.crossbar import LiteEthCrossbar

diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py
index 9baa0c9fd486268499b2ea43fdadcdddc22320eb..d5bf2f93471392eb54168c414e80cbb6dc7f3ede 100644 (file)
--- a/liteeth/mac/core/__init__.py
+++ b/liteeth/mac/core/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac.core import gap, preamble, crc, last_be
 
 class LiteEthMACCore(Module, AutoCSR):

diff --git a/liteeth/mac/core/crc.py b/liteeth/mac/core/crc.py
index b14d0a125c17344656ade22c30dbeb226d8034f5..80321e4cbd42c3f151db31a183b360d8ab1d71b4 100644 (file)
--- a/liteeth/mac/core/crc.py
+++ b/liteeth/mac/core/crc.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACCRCEngine(Module):
        """Cyclic Redundancy Check Engine

diff --git a/liteeth/mac/core/gap.py b/liteeth/mac/core/gap.py
index 0f1ddd7911f9ae002c2287b6d00ab69a03156d98..84f738aac067997a276d31fb16f11977750722f7 100644 (file)
--- a/liteeth/mac/core/gap.py
+++ b/liteeth/mac/core/gap.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACGap(Module):
        def __init__(self, dw, ack_on_gap=False):

diff --git a/liteeth/mac/core/last_be.py b/liteeth/mac/core/last_be.py
index 7d82b934b3bb5704aeeb998d4355fc05fe8f4018..2b67ad45d24b56b3ad86445beb2b2611f8bfa70a 100644 (file)
--- a/liteeth/mac/core/last_be.py
+++ b/liteeth/mac/core/last_be.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACTXLastBE(Module):
        def __init__(self, dw):

diff --git a/liteeth/mac/core/preamble.py b/liteeth/mac/core/preamble.py
index 1b9f033c676e51bc549cb378fb46f2f0277720aa..fd3cb97528ebdb8f764fc959cf4a18e563a1df4c 100644 (file)
--- a/liteeth/mac/core/preamble.py
+++ b/liteeth/mac/core/preamble.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACPreambleInserter(Module):
        def __init__(self, dw):

diff --git a/liteeth/mac/frontend/sram.py b/liteeth/mac/frontend/sram.py
index eefb9a6234880a9fe461c6e9eeaf9db550d658e7..cffe71b405789ed0e1dee2d5ff67e30f392c9b1a 100644 (file)
--- a/liteeth/mac/frontend/sram.py
+++ b/liteeth/mac/frontend/sram.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 from migen.bank.description import *
 from migen.bank.eventmanager import *

diff --git a/liteeth/mac/frontend/wishbone.py b/liteeth/mac/frontend/wishbone.py
index 71b467dfa0f1953bff70a52d60c4a36861db47f5..a68fe382d56c2178ed1d2ab9c05c34a87da97b88 100644 (file)
--- a/liteeth/mac/frontend/wishbone.py
+++ b/liteeth/mac/frontend/wishbone.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac.frontend import sram
 
 from migen.bus import wishbone

diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py
index 1388704b446fa80f74327675e264dd8fcde93aad..180f7da59fc58502a8a888ac2bcb3d65103a0f7e 100644 (file)
--- a/liteeth/phy/gmii.py
+++ b/liteeth/phy/gmii.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthPHYGMIITX(Module):
        def __init__(self, pads):

diff --git a/liteeth/phy/loopback.py b/liteeth/phy/loopback.py
index 3f5ccf0ac1c4d4010861cde86be2c54d8969e812..89ffcb3a06d5bee6ee55d14a8486a9b20944e568 100644 (file)
--- a/liteeth/phy/loopback.py
+++ b/liteeth/phy/loopback.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthPHYLoopbackCRG(Module, AutoCSR):
        def __init__(self):

diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py
index 1dfda43a1ebdf4f5f92a3af055f071c827691179..0d3f61be6d52339af5e13ad95adaeeba7e20a0d4 100644 (file)
--- a/liteeth/phy/mii.py
+++ b/liteeth/phy/mii.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthPHYMIITX(Module):
        def __init__(self, pads):