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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index a3e3c7a890e399459f8c88b49a3d44f0f3354d17..3a6919033dffc22786946325f3505154cb09aa90 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -109,10 +109,6 @@ Examples of the former type:
   With `CRbit` coming from the SVP64 RM bits 22-23 the bit
   of BF to be tested is identified.
 
-This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
-Mode. This is unfortunste but unavoidable due to encoding pressure
-on SVP64.
-
 # Predicate-result Condition Register operations
 
 These are again slightly different compared to SVP64 arithmetic