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diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index e3ad496b5ba1f067b0775d6c7f392b82523be5e7..6816a9aeae79a33f0066ec1cac15130e2019f79e 100644 (file)
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -10,7 +10,7 @@ Walkthrough video: <https://youtu.be/6Yiyw4abJpE>
 
 Basic diagram:
 
-[[!img 180nm_single_core_testasic_memlayout.jpg size="600x"]]
+[[!img 180nm_single_core_test_asic_memlayout_F1.svg size="1063x"]]
 
 * Eight LD/ST Function Units with 2 ports each (one for aligned,
   one for misaligned), each connecting to one of a pair of L0