update comments and correct retiring, remove registers that have been written

diff --git a/src/openpower/cyclemodel/inorder.py b/src/openpower/cyclemodel/inorder.py
index 42176990b13662af8c6e40c0280a26f5b9b03c74..5d311c69a14b59b0e56b68382a1129af2ecfd82c 100644 (file)
--- a/src/openpower/cyclemodel/inorder.py
+++ b/src/openpower/cyclemodel/inorder.py
@@ -2,11 +2,22 @@
 # An In-order cycle-accurate model of a Power ISA 3.0 hardware implementation
 
 class RegisterWrite(set):
+    """RegisterWrite: contains the set of Read-after-Write Hazards.
+    Anything in this set must be a STALL at Decode phase because the
+    answer has still not popped out the end of a pipeline
+    """
     def expect_write(self, regs): self.update(regs)
     def write_expected(self, regs): len(self.intersection(regs)) != 0
     def retire_write(self, regs): self.difference_update(regs)
 
 class Execute:
+    """Execute Pipeline: keeps a countdown-sorted list of instructions
+    to expect at a future cycle (tick).  Anything at zero is processed
+    by assuming it is completed, and wishes to write to the regfile.
+    However there are only a limited number of regfile write ports,
+    so they must be handled a few at a time.  under these circumstances
+    STALL condition is returned, and the "processor" must *NOT* tick().
+    """
     def __init__(self, cpu):
         self.stages = []
         self.cpu = cpu
@@ -33,5 +44,8 @@ class Execute:
         if writes_possible != to_write:
             stall = True
         # retire the writes that are possible in this cycle (regfile writes)
-        self.cpu.regs.retire_write(to_write)
+        self.cpu.regs.retire_write(writes_possible)
+        # and now go through the instructions, removing those regs written
+        for instruction in instructions:
+            instruction['writes'].difference_update(writes_possible)
         return stall