power_insn: support ew specifier

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 2007aadeee631390eb44cdaaccf3060fedf634e3..d092bd16f9ca90a6fa001e3acae14a474e47d4bc 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1301,7 +1301,18 @@ class BaseRM(_Mapping):
 
 
 class NormalBaseRM(BaseRM):
-    pass
+    @property
+    def specifiers(self):
+        ew = int(self.elwidth)
+        if ew != 0b00:
+            ew = {
+                0b11: "8",
+                0b10: "16",
+                0b01: "32",
+            }[ew]
+            yield f"ew={ew}"
+
+        yield from super().specifiers
 
 
 class NormalSimpleRM(NormalBaseRM):
@@ -1417,7 +1428,18 @@ class NormalRM(NormalBaseRM):
 
 
 class LDSTImmBaseRM(BaseRM):
-    pass
+    @property
+    def specifiers(self):
+        ew = int(self.elwidth)
+        if ew != 0b00:
+            ew = {
+                0b11: "8",
+                0b10: "16",
+                0b01: "32",
+            }[ew]
+            yield f"ew={ew}"
+
+        yield from super().specifiers
 
 
 class LDSTImmSimpleRM(LDSTImmBaseRM):
@@ -1489,7 +1511,18 @@ class LDSTImmRM(LDSTImmBaseRM):
 
 
 class LDSTIdxBaseRM(BaseRM):
-    pass
+    @property
+    def specifiers(self):
+        ew = int(self.elwidth)
+        if ew != 0b00:
+            ew = {
+                0b11: "8",
+                0b10: "16",
+                0b01: "32",
+            }[ew]
+            yield f"ew={ew}"
+
+        yield from super().specifiers
 
 
 class LDSTIdxSimpleRM(LDSTIdxBaseRM):