ARM: Add support for DIV/SDIV instructions.

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b8a047f6501756de7c215d8465f5650d887ca61f..25bc3161b97da019664966bbbbd35f0f5d84a468 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -140,7 +140,7 @@ ISA::clear()
 
     // See section B4.1.84 of ARM ARM
     // All values are latest for ARMv7-A profile
-    miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
+    miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
     miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
     miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
     miscRegs[MISCREG_ID_ISAR3] = 0x01112131;

diff --git a/src/arch/arm/isa/formats/mult.isa b/src/arch/arm/isa/formats/mult.isa
index cfd00b1a5cabeba4db93119942d3a0443e4fef40..73157dd57472a39c4e6a863695c3edb76511d36f 100644 (file)
--- a/src/arch/arm/isa/formats/mult.isa
+++ b/src/arch/arm/isa/formats/mult.isa
@@ -394,6 +394,16 @@ def format ArmSignedMultiplies() {{
                 }
             }
             break;
+          case 0x1:
+            if (op2 == 0 && m == 0 && ra == 0xf) {
+                return new Sdiv(machInst, rd, rn, rm);
+            }
+            break;
+          case 0x3:
+            if (op2 == 0 && m == 0 && ra == 0xf) {
+                return new Udiv(machInst, rd, rn, rm);
+            }
+            break;
           case 0x4:
             if (op2 == 0) {
                 if (m) {