altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.

diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
index 252f5fbd4277c04a273c7ad52a6c3d207f003561..e9adf2a3238330f8252bc1732a55dba53bc1e523 100644 (file)
--- a/litex/build/altera/common.py
+++ b/litex/build/altera/common.py
@@ -9,7 +9,35 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.build.io import *
 
-# DifferentialInput --------------------------------------------------------------------------------
+# Common AsyncResetSynchronizer --------------------------------------------------------------------
+
+class AlteraAsyncResetSynchronizerImpl(Module):
+    def __init__(self, cd, async_reset):
+        rst_meta = Signal()
+        self.specials += [
+            Instance("DFF",
+                i_d    = 0,
+                i_clk  = cd.clk,
+                i_clrn = 1,
+                i_prn  = ~async_reset,
+                o_q    = rst_meta
+            ),
+            Instance("DFF",
+                i_d    = rst_meta,
+                i_clk  = cd.clk,
+                i_clrn = 1,
+                i_prn  = ~async_reset,
+                o_q    = cd.rst
+            )
+        ]
+
+
+class AlteraAsyncResetSynchronizer:
+    @staticmethod
+    def lower(dr):
+        return AlteraAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
+
+# Common DifferentialInput -------------------------------------------------------------------------
 
 class AlteraDifferentialInputImpl(Module):
     def __init__(self, i_p, i_n, o):
@@ -28,7 +56,7 @@ class AlteraDifferentialInput:
     def lower(dr):
         return AlteraDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
 
-# DifferentialOutput -------------------------------------------------------------------------------
+# Common DifferentialOutput ------------------------------------------------------------------------
 
 class AlteraDifferentialOutputImpl(Module):
     def __init__(self, i, o_p, o_n):
@@ -47,38 +75,63 @@ class AlteraDifferentialOutput:
     def lower(dr):
         return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
 
-# AsyncResetSynchronizer ---------------------------------------------------------------------------
+# Common DDROutput ---------------------------------------------------------------------------------
 
-class AlteraAsyncResetSynchronizerImpl(Module):
-    def __init__(self, cd, async_reset):
-        rst_meta = Signal()
-        self.specials += [
-            Instance("DFF",
-                i_d    = 0,
-                i_clk  = cd.clk,
-                i_clrn = 1,
-                i_prn  = ~async_reset,
-                o_q    = rst_meta
-            ),
-            Instance("DFF",
-                i_d    = rst_meta,
-                i_clk  = cd.clk,
-                i_clrn = 1,
-                i_prn  = ~async_reset,
-                o_q    = cd.rst
-            )
-        ]
+class AlteraDDROutputImpl(Module):
+    def __init__(self, i1, i2, o, clk):
+        self.specials += Instance("ALTDDIO_OUT",
+            p_WIDTH    = 1,
+            i_outclock = clk,
+            i_datain_h = i1,
+            i_datain_l = i2,
+            o_dataout  = o,
+        )
 
 
-class AlteraAsyncResetSynchronizer:
+class AlteraDDROutput:
     @staticmethod
     def lower(dr):
-        return AlteraAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
+        return AlteraDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
+
+# Common DDRInput ----------------------------------------------------------------------------------
+
+class AlteraDDRInputImpl(Module):
+    def __init__(self, i, o1, o2, clk):
+        self.specials += Instance("ALTDDIO_IN",
+            p_WIDTH     = 1,
+            i_inclock   = clk,
+            i_datain    = i,
+            o_dataout_h = o1,
+            o_dataout_l = o2
+        )
+
+class AlteraDDRInput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
+
+# Common SDROutput -------------------------------------------------------------------------------
+
+class AlteraSDROutput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDDROutputImpl(dr.i, dr.i, dr.o, dr.clk)
+
+# Common SDRInput --------------------------------------------------------------------------------
+
+class AlteraSDRInput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
 
 # Special Overrides --------------------------------------------------------------------------------
 
 altera_special_overrides = {
+    AsyncResetSynchronizer: AlteraAsyncResetSynchronizer,
     DifferentialInput:      AlteraDifferentialInput,
     DifferentialOutput:     AlteraDifferentialOutput,
-    AsyncResetSynchronizer: AlteraAsyncResetSynchronizer,
+    DDROutput:              AlteraDDROutput,
+    DDRInput:               AlteraDDRInput,
+    SDROutput:              AlteraSDROutput,
+    SDRInput:               AlteraSDRInput,
 }