Automatically select new objects in abc and techmap passes

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 2fd3334c432162c4b1024c0331c86a61a5f9e635..a51557a4ee085c546bd6ea20d15fb6d0c9cd701a 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -459,6 +459,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                        RTLIL::Wire *wire = new RTLIL::Wire;
                        wire->name = remap_name(w->name);
                        module->wires[wire->name] = wire;
+                       design->select(module, wire);
                }
 
                std::map<std::string, int> cell_stats;
@@ -488,6 +489,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                                        cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]);
                                        cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
                                        module->cells[cell->name] = cell;
+                                       design->select(module, cell);
                                        continue;
                                }
                                if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
@@ -498,6 +500,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                                        cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks[0].wire->name)]);
                                        cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
                                        module->cells[cell->name] = cell;
+                                       design->select(module, cell);
                                        continue;
                                }
                                if (c->type == "\\MUX") {
@@ -509,6 +512,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                                        cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks[0].wire->name)]);
                                        cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
                                        module->cells[cell->name] = cell;
+                                       design->select(module, cell);
                                        continue;
                                }
                                assert(0);
@@ -532,6 +536,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                                for (auto &conn : c->connections)
                                        cell->connections[conn.first] = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
                                module->cells[cell->name] = cell;
+                               design->select(module, cell);
                        }
                }
 

diff --git a/passes/opt/opt_rmunused.cc b/passes/opt/opt_rmunused.cc
index 4807a97b6a4fd03e0df9fe5790e38ac61e3076a8..3276ad6264b74a2beeb43b03c84377404b72c5a3 100644 (file)
--- a/passes/opt/opt_rmunused.cc
+++ b/passes/opt/opt_rmunused.cc
@@ -118,6 +118,17 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
        return w2->name < w1->name;
 }
 
+static bool check_public_name(RTLIL::IdString id)
+{
+       if (id[0] == '$')
+               return false;
+#if 0
+       if (id.find(".$") == std::string::npos)
+               return true;
+#endif
+       return false;
+}
+
 static void rmunused_module_signals(RTLIL::Module *module)
 {
        SigMap assign_map(module);
@@ -157,7 +168,7 @@ static void rmunused_module_signals(RTLIL::Module *module)
        std::vector<RTLIL::Wire*> del_wires;
        for (auto &it : module->wires) {
                RTLIL::Wire *wire = it.second;
-               if (wire->name[0] == '\\') {
+               if (check_public_name(wire->name)) {
                        RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
                        assign_map.apply(s2);
                        if (!used_signals.check_any(s2) && wire->port_id == 0) {

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index d959dbe1d8638f66bd9181ab7de58868788e7b43..c05a96cd40a7ad8a46c4ea4f310f7d817dd41f86 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -112,6 +112,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
                        w->port_output = false;
                        w->port_id = 0;
                        module->wires[w->name] = w;
+                       design->select(module, w);
                }
 
                for (auto &it : tpl->cells) {
@@ -122,6 +123,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
                        for (auto &it2 : c->connections)
                                apply_prefix(cell_name, it2.second, module);
                        module->cells[c->name] = c;
+                       design->select(module, c);
                }
 
                for (auto &it : tpl->connections) {