freedreno/a6xx: blitter fixes
authorRob Clark <robdclark@gmail.com>
Mon, 3 Dec 2018 15:27:32 +0000 (10:27 -0500)
committerRob Clark <robdclark@gmail.com>
Fri, 7 Dec 2018 18:49:21 +0000 (13:49 -0500)
Signed-off-by: Rob Clark <robdclark@gmail.com>
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
src/gallium/drivers/freedreno/a6xx/fd6_format.h

index 30840955b61cb8554f7ed3082b04e6c5c1c990b0..13a5e4afb436b3d1167ca36a2ebef19502b5a5ad 100644 (file)
@@ -47,7 +47,6 @@ ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
                r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
                : r->array_size;
 
-
        return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
                (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
                (b->z >= 0) && (b->z + b->depth <= last_layer);
@@ -139,6 +138,15 @@ emit_setup(struct fd_ringbuffer *ring)
        OUT_RING(ring, 0x10000000);
 }
 
+static uint32_t
+blit_control(enum a6xx_color_fmt fmt)
+{
+       unsigned blit_cntl = 0xf00000;
+       blit_cntl |= A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt);
+       blit_cntl |= A6XX_RB_2D_BLIT_CNTL_IFMT(fd6_ifmt(fmt));
+       return blit_cntl;
+}
+
 /* buffers need to be handled specially since x/width can exceed the bounds
  * supported by hw.. if necessary decompose into (potentially) two 2D blits
  */
@@ -198,7 +206,7 @@ emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
        OUT_PKT7(ring, CP_SET_MARKER, 1);
        OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
 
-       uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R8_UNORM) | 0x20f00000;
+       uint32_t blit_cntl = blit_control(RB6_R8_UNORM) | 0x20000000;
        OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
        OUT_RING(ring, blit_cntl);
 
@@ -374,7 +382,7 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
        OUT_PKT7(ring, CP_SET_MARKER, 1);
        OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
 
-       uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(dfmt) | 0xf00000;
+       uint32_t blit_cntl = blit_control(dfmt);
 
        if (dtile != stile)
                blit_cntl |= 0x20000000;
index 6f96256fa85e2eb9c35baa157362cbcc3c6d63e6..56166dc4505d688784ae7cf9404127c1fc1ac1a8 100644 (file)
@@ -42,4 +42,73 @@ enum a6xx_depth_format fd6_pipe2depth(enum pipe_format format);
 uint32_t fd6_tex_swiz(enum pipe_format format, unsigned swizzle_r,
                unsigned swizzle_g, unsigned swizzle_b, unsigned swizzle_a);
 
+static inline enum a6xx_2d_ifmt
+fd6_ifmt(enum a6xx_color_fmt fmt)
+{
+       switch (fmt) {
+       case RB6_A8_UNORM:
+       case RB6_R8_UNORM:
+       case RB6_R8_SNORM:
+       case RB6_R8G8_UNORM:
+       case RB6_R8G8_SNORM:
+       case RB6_R8G8B8A8_UNORM:
+       case RB6_R8G8B8_UNORM:
+       case RB6_R8G8B8A8_SNORM:
+               return R2D_UNORM8;
+
+       case RB6_R32_UINT:
+       case RB6_R32_SINT:
+       case RB6_R32G32_UINT:
+       case RB6_R32G32_SINT:
+       case RB6_R32G32B32A32_UINT:
+       case RB6_R32G32B32A32_SINT:
+               return R2D_INT32;
+
+       case RB6_R16_UINT:
+       case RB6_R16_SINT:
+       case RB6_R16G16_UINT:
+       case RB6_R16G16_SINT:
+       case RB6_R16G16B16A16_UINT:
+       case RB6_R16G16B16A16_SINT:
+               return R2D_INT16;
+
+       case RB6_R8_UINT:
+       case RB6_R8_SINT:
+       case RB6_R8G8_UINT:
+       case RB6_R8G8_SINT:
+       case RB6_R8G8B8A8_UINT:
+       case RB6_R8G8B8A8_SINT:
+               return R2D_INT8;
+
+       case RB6_R16_UNORM:
+       case RB6_R16_SNORM:
+       case RB6_R16G16_UNORM:
+       case RB6_R16G16_SNORM:
+       case RB6_R16G16B16A16_UNORM:
+       case RB6_R16G16B16A16_SNORM:
+       case RB6_R32_FLOAT:
+       case RB6_R32G32_FLOAT:
+       case RB6_R32G32B32A32_FLOAT:
+               return R2D_FLOAT32;
+
+       case RB6_R16_FLOAT:
+       case RB6_R16G16_FLOAT:
+       case RB6_R16G16B16A16_FLOAT:
+               return R2D_FLOAT16;
+
+       case RB6_R4G4B4A4_UNORM:
+       case RB6_R5G5B5A1_UNORM:
+       case RB6_R5G6B5_UNORM:
+       case RB6_R10G10B10A2_UNORM:
+       case RB6_R10G10B10A2_UINT:
+       case RB6_R11G11B10_FLOAT:
+       case RB6_X8Z24_UNORM:
+               // ???
+               return 0;
+       default:
+               unreachable("bad format");
+               return 0;
+       }
+}
+
 #endif /* FD6_UTIL_H_ */