[NDS32] Generate alu-shift instructions only for -Os.
authorChung-Ju Wu <jasonwucj@gmail.com>
Thu, 5 Apr 2018 03:10:42 +0000 (03:10 +0000)
committerChung-Ju Wu <jasonwucj@gcc.gnu.org>
Thu, 5 Apr 2018 03:10:42 +0000 (03:10 +0000)
gcc/
* config/nds32/nds32.md: Use optimize_size in the condition for
alu-shift instructions.

From-SVN: r259120

gcc/ChangeLog
gcc/config/nds32/nds32.md

index 485c59ea79761d20655b97f1e4d8ac563d5a433a..0928418e9eadc60dcf8891b0971ffb45543ec8a1 100644 (file)
@@ -1,3 +1,8 @@
+2018-04-05  Chung-Ju Wu  <jasonwucj@gmail.com>
+
+       * config/nds32/nds32.md: Use optimize_size in the condition for
+       alu-shift instructions.
+
 2018-04-05  Chung-Ju Wu  <jasonwucj@gmail.com>
 
        * config/nds32/nds32.md (divsi4, udivsi4): New patterns.
index 2d0f1d3e91bf70507b5f210ab6731b40713b5365..b64e1c20bf9ac3fdaebb62cc4930bb1e4b5aeff7 100644 (file)
        (plus:SI (mult:SI (match_operand:SI 1 "register_operand"  " r")
                          (match_operand:SI 2 "immediate_operand" " i"))
                 (match_operand:SI 3 "register_operand"           " r")))]
-  "TARGET_ISA_V3
+  "TARGET_ISA_V3 && optimize_size
    && (exact_log2 (INTVAL (operands[2])) != -1)
    && (exact_log2 (INTVAL (operands[2])) <= 31)"
 {
        (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"    "    r")
                              (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
                 (match_operand:SI 3 "register_operand"                 "    r")))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "add_srli\t%0, %3, %1, %2"
   [(set_attr "type" "alu_shift")
    (set_attr "combo"        "2")
        (minus:SI (match_operand:SI 1 "register_operand"           " r")
                  (mult:SI (match_operand:SI 2 "register_operand"  " r")
                           (match_operand:SI 3 "immediate_operand" " i"))))]
-  "TARGET_ISA_V3
+  "TARGET_ISA_V3 && optimize_size
    && (exact_log2 (INTVAL (operands[3])) != -1)
    && (exact_log2 (INTVAL (operands[3])) <= 31)"
 {
        (minus:SI (match_operand:SI 1 "register_operand"                 "    r")
                  (lshiftrt:SI (match_operand:SI 2 "register_operand"    "    r")
                               (match_operand:SI 3 "nds32_imm5u_operand" " Iu05"))))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "sub_srli\t%0, %1, %2, %3"
   [(set_attr "type" "alu_shift")
    (set_attr "combo"        "2")
        (and:SI (ashift:SI (match_operand:SI 1 "register_operand"     "    r")
                            (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
                (match_operand:SI 3 "register_operand"                "    r")))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "and_slli\t%0, %3, %1, %2"
   [(set_attr "type" "alu_shift")
    (set_attr "length"       "4")])
        (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"    "    r")
                             (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
                (match_operand:SI 3 "register_operand"                 "    r")))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "and_srli\t%0, %3, %1, %2"
   [(set_attr "type" "alu_shift")
    (set_attr "length"       "4")])
        (ior:SI (ashift:SI (match_operand:SI 1 "register_operand"    "    r")
                           (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
                (match_operand:SI 3 "register_operand"               "    r")))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "or_slli\t%0, %3, %1, %2"
   [(set_attr "type" "alu_shift")
    (set_attr "length"       "4")])
        (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"    "    r")
                             (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
                (match_operand:SI 3 "register_operand"                 "    r")))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "or_srli\t%0, %3, %1, %2"
   [(set_attr "type" "alu_shift")
    (set_attr "length"       "4")])
        (xor:SI (ashift:SI (match_operand:SI 1 "register_operand"  "    r")
                           (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
                (match_operand:SI 3 "register_operand"             "    r")))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "xor_slli\t%0, %3, %1, %2"
   [(set_attr "type" "alu_shift")
    (set_attr "length"       "4")])
        (xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand"    "    r")
                             (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
                (match_operand:SI 3 "register_operand"                 "    r")))]
-  "TARGET_ISA_V3"
+  "TARGET_ISA_V3 && optimize_size"
   "xor_srli\t%0, %3, %1, %2"
   [(set_attr "type" "alu_shift")
    (set_attr "length"       "4")])