projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
840bb17
)
Supress error for unhandled \init if whole module selected
author
Eddie Hung
<eddie@fpgeh.com>
Wed, 11 Dec 2019 19:49:13 +0000
(11:49 -0800)
committer
Eddie Hung
<eddie@fpgeh.com>
Mon, 13 Apr 2020 20:16:49 +0000
(13:16 -0700)
passes/techmap/zinit.cc
patch
|
blob
|
history
diff --git
a/passes/techmap/zinit.cc
b/passes/techmap/zinit.cc
index a427c498753fa3053a4be76fdd449e094cf12337..5cfc82ac902f26ab622c1c3ba203e67ad4c07f27 100644
(file)
--- a/
passes/techmap/zinit.cc
+++ b/
passes/techmap/zinit.cc
@@
-141,9
+141,10
@@
struct ZinitPass : public Pass {
cell->setPort(ID::Q, initwire);
}
- for (auto &it : initbits)
- if (donebits.count(it.first) == 0)
- log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
+ if (!design->selected_whole_module(module))
+ for (auto &it : initbits)
+ if (donebits.count(it.first) == 0)
+ log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
}
}
} ZinitPass;