Work in progress for renaming labels/options in synth_xilinx

diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
deleted file mode 100644 (file)
index 2613c20..0000000
--- a/techlibs/xilinx/drams.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-
-bram $__XILINX_RAM32X1D
-  init 1
-  abits 5
-  dbits 1
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 0 1
-  transp 0 0
-  clocks 0 1
-  clkpol 0 2
-endbram
-
-bram $__XILINX_RAM64X1D
-  init 1
-  abits 6
-  dbits 1
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 0 1
-  transp 0 0
-  clocks 0 1
-  clkpol 0 2
-endbram
-
-bram $__XILINX_RAM128X1D
-  init 1
-  abits 7
-  dbits 1
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 0 1
-  transp 0 0
-  clocks 0 1
-  clkpol 0 2
-endbram
-
-match $__XILINX_RAM32X1D
-  min bits 3
-  min wports 1
-  make_outreg
-  or_next_if_better
-endmatch
-
-match $__XILINX_RAM64X1D
-  min bits 5
-  min wports 1
-  make_outreg
-  or_next_if_better
-endmatch
-
-match $__XILINX_RAM128X1D
-  min bits 9
-  min wports 1
-  make_outreg
-endmatch
-

diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v
deleted file mode 100644 (file)
index 77041ca..0000000
--- a/techlibs/xilinx/drams_map.v
+++ /dev/null
@@ -1,97 +0,0 @@
-
-module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
-       parameter [31:0] INIT = 32'bx;
-       parameter CLKPOL2 = 1;
-       input CLK1;
-
-       input [4:0] A1ADDR;
-       output A1DATA;
-
-       input [4:0] B1ADDR;
-       input B1DATA;
-       input B1EN;
-
-       RAM32X1D #(
-               .INIT(INIT),
-               .IS_WCLK_INVERTED(!CLKPOL2)
-       ) _TECHMAP_REPLACE_ (
-               .DPRA0(A1ADDR[0]),
-               .DPRA1(A1ADDR[1]),
-               .DPRA2(A1ADDR[2]),
-               .DPRA3(A1ADDR[3]),
-               .DPRA4(A1ADDR[4]),
-               .DPO(A1DATA),
-
-               .A0(B1ADDR[0]),
-               .A1(B1ADDR[1]),
-               .A2(B1ADDR[2]),
-               .A3(B1ADDR[3]),
-               .A4(B1ADDR[4]),
-               .D(B1DATA),
-               .WCLK(CLK1),
-               .WE(B1EN)
-       );
-endmodule
-
-module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
-       parameter [63:0] INIT = 64'bx;
-       parameter CLKPOL2 = 1;
-       input CLK1;
-
-       input [5:0] A1ADDR;
-       output A1DATA;
-
-       input [5:0] B1ADDR;
-       input B1DATA;
-       input B1EN;
-
-       RAM64X1D #(
-               .INIT(INIT),
-               .IS_WCLK_INVERTED(!CLKPOL2)
-       ) _TECHMAP_REPLACE_ (
-               .DPRA0(A1ADDR[0]),
-               .DPRA1(A1ADDR[1]),
-               .DPRA2(A1ADDR[2]),
-               .DPRA3(A1ADDR[3]),
-               .DPRA4(A1ADDR[4]),
-               .DPRA5(A1ADDR[5]),
-               .DPO(A1DATA),
-
-               .A0(B1ADDR[0]),
-               .A1(B1ADDR[1]),
-               .A2(B1ADDR[2]),
-               .A3(B1ADDR[3]),
-               .A4(B1ADDR[4]),
-               .A5(B1ADDR[5]),
-               .D(B1DATA),
-               .WCLK(CLK1),
-               .WE(B1EN)
-       );
-endmodule
-
-module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
-       parameter [127:0] INIT = 128'bx;
-       parameter CLKPOL2 = 1;
-       input CLK1;
-
-       input [6:0] A1ADDR;
-       output A1DATA;
-
-       input [6:0] B1ADDR;
-       input B1DATA;
-       input B1EN;
-
-       RAM128X1D #(
-               .INIT(INIT),
-               .IS_WCLK_INVERTED(!CLKPOL2)
-       ) _TECHMAP_REPLACE_ (
-               .DPRA(A1ADDR),
-               .DPO(A1DATA),
-
-               .A(B1ADDR),
-               .D(B1DATA),
-               .WCLK(CLK1),
-               .WE(B1EN)
-       );
-endmodule
-

diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt
new file mode 100644 (file)
index 0000000..2613c20
--- /dev/null
+++ b/techlibs/xilinx/lutrams.txt
@@ -0,0 +1,60 @@
+
+bram $__XILINX_RAM32X1D
+  init 1
+  abits 5
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+bram $__XILINX_RAM64X1D
+  init 1
+  abits 6
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+bram $__XILINX_RAM128X1D
+  init 1
+  abits 7
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+match $__XILINX_RAM32X1D
+  min bits 3
+  min wports 1
+  make_outreg
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAM64X1D
+  min bits 5
+  min wports 1
+  make_outreg
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAM128X1D
+  min bits 9
+  min wports 1
+  make_outreg
+endmatch
+

diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v
new file mode 100644 (file)
index 0000000..77041ca
--- /dev/null
+++ b/techlibs/xilinx/lutrams_map.v
@@ -0,0 +1,97 @@
+
+module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+       parameter [31:0] INIT = 32'bx;
+       parameter CLKPOL2 = 1;
+       input CLK1;
+
+       input [4:0] A1ADDR;
+       output A1DATA;
+
+       input [4:0] B1ADDR;
+       input B1DATA;
+       input B1EN;
+
+       RAM32X1D #(
+               .INIT(INIT),
+               .IS_WCLK_INVERTED(!CLKPOL2)
+       ) _TECHMAP_REPLACE_ (
+               .DPRA0(A1ADDR[0]),
+               .DPRA1(A1ADDR[1]),
+               .DPRA2(A1ADDR[2]),
+               .DPRA3(A1ADDR[3]),
+               .DPRA4(A1ADDR[4]),
+               .DPO(A1DATA),
+
+               .A0(B1ADDR[0]),
+               .A1(B1ADDR[1]),
+               .A2(B1ADDR[2]),
+               .A3(B1ADDR[3]),
+               .A4(B1ADDR[4]),
+               .D(B1DATA),
+               .WCLK(CLK1),
+               .WE(B1EN)
+       );
+endmodule
+
+module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+       parameter [63:0] INIT = 64'bx;
+       parameter CLKPOL2 = 1;
+       input CLK1;
+
+       input [5:0] A1ADDR;
+       output A1DATA;
+
+       input [5:0] B1ADDR;
+       input B1DATA;
+       input B1EN;
+
+       RAM64X1D #(
+               .INIT(INIT),
+               .IS_WCLK_INVERTED(!CLKPOL2)
+       ) _TECHMAP_REPLACE_ (
+               .DPRA0(A1ADDR[0]),
+               .DPRA1(A1ADDR[1]),
+               .DPRA2(A1ADDR[2]),
+               .DPRA3(A1ADDR[3]),
+               .DPRA4(A1ADDR[4]),
+               .DPRA5(A1ADDR[5]),
+               .DPO(A1DATA),
+
+               .A0(B1ADDR[0]),
+               .A1(B1ADDR[1]),
+               .A2(B1ADDR[2]),
+               .A3(B1ADDR[3]),
+               .A4(B1ADDR[4]),
+               .A5(B1ADDR[5]),
+               .D(B1DATA),
+               .WCLK(CLK1),
+               .WE(B1EN)
+       );
+endmodule
+
+module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+       parameter [127:0] INIT = 128'bx;
+       parameter CLKPOL2 = 1;
+       input CLK1;
+
+       input [6:0] A1ADDR;
+       output A1DATA;
+
+       input [6:0] B1ADDR;
+       input B1DATA;
+       input B1EN;
+
+       RAM128X1D #(
+               .INIT(INIT),
+               .IS_WCLK_INVERTED(!CLKPOL2)
+       ) _TECHMAP_REPLACE_ (
+               .DPRA(A1ADDR),
+               .DPO(A1DATA),
+
+               .A(B1ADDR),
+               .D(B1DATA),
+               .WCLK(CLK1),
+               .WE(B1EN)
+       );
+endmodule
+

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b672a0d4f5f50a42a037d86f16a6717c5308c8c8..a6c1fa873d18b802e26797c52169a39fe765c199 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -64,13 +64,13 @@ struct SynthXilinxPass : public ScriptPass
                log("        (this feature is experimental and incomplete)\n");
                log("\n");
                log("    -nobram\n");
-               log("        disable inference of block rams\n");
+               log("        do not use block RAM cells in output netlist\n");
                log("\n");
-               log("    -nodram\n");
-               log("        disable inference of distributed rams\n");
+               log("    -nolutram\n");
+               log("        do not use distributed RAM cells in output netlist\n");
                log("\n");
                log("    -nosrl\n");
-               log("        disable inference of shift registers\n");
+               log("        do not use distributed SRL cells in output netlist\n");
                log("\n");
                log("    -nocarry\n");
                log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
@@ -104,7 +104,7 @@ struct SynthXilinxPass : public ScriptPass
        }
 
        std::string top_opt, edif_file, blif_file, family;
-       bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
+       bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
        int widemux;
 
        void clear_flags() YS_OVERRIDE
@@ -118,7 +118,7 @@ struct SynthXilinxPass : public ScriptPass
                vpr = false;
                nocarry = false;
                nobram = false;
-               nodram = false;
+               nolutram = false;
                nosrl = false;
                nocarry = false;
                nowidelut = false;
@@ -186,8 +186,8 @@ struct SynthXilinxPass : public ScriptPass
                                nobram = true;
                                continue;
                        }
-                       if (args[argidx] == "-nodram") {
-                               nodram = true;
+                       if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+                               nolutram = true;
                                continue;
                        }
                        if (args[argidx] == "-nosrl") {
@@ -284,7 +284,7 @@ struct SynthXilinxPass : public ScriptPass
                        run("opt_clean");
                }
 
-               if (check_label("bram", "(skip if '-nobram')")) {
+               if (check_label("map_bram", "(skip if '-nobram')")) {
                        if (help_mode) {
                                run("memory_bram -rules +/xilinx/{family}_brams.txt");
                                run("techmap -map +/xilinx/{family}_brams_map.v");
@@ -301,20 +301,23 @@ struct SynthXilinxPass : public ScriptPass
                        }
                }
 
-               if (check_label("dram", "(skip if '-nodram')")) {
-                       if (!nodram || help_mode) {
-                               run("memory_bram -rules +/xilinx/drams.txt");
-                               run("techmap -map +/xilinx/drams_map.v");
+               if (check_label("map_lutram", "(skip if '-nolutram')")) {
+                       if (!nolutram || help_mode) {
+                               run("memory_bram -rules +/xilinx/lutrams.txt");
+                               run("techmap -map +/xilinx/lutrams_map.v");
                        }
                }
 
-               if (check_label("fine")) {
+               if (check_label("map_ffram")) {
                        if (widemux > 0)
                                run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
                                                                            // performs less efficiently
                        else
                                run("opt -fast -full");
                        run("memory_map");
+               }
+
+               if (check_label("fine")) {
                        run("dffsr2dff");
                        run("dff2dffe");
                        if (help_mode) {