missed rlwm* in conversion to RC_ONLY

diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv
index d06d5a39ca26b5bf46d93c1cd0110eb479102391..14e3f1bfd1fdd7ff66d00586ee3590f9195954fb 100644 (file)
--- a/openpower/isatables/major.csv
+++ b/openpower/isatables/major.csv
@@ -25,9 +25,9 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D,
 24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D,
 25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D,
-20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi,M,
-21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm,M,
-23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm,M,
+20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,rlwimi,M,
+21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,rlwinm,M,
+23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,rlwnm,M,
 38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,D,
 39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,D,
 54,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stfd,D,