continue;
}
- fprintf(f, ".%s %s", subckt_or_gate(cell->type), cstr(cell->type));
+ fprintf(f, ".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
for (auto &conn : cell->connections())
for (int i = 0; i < conn.second.size(); i++) {
if (conn.second.size() == 1)
{
cell_line = ++line_num;
bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true;
- str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type).c_str(), reduced?output_width:w, l);
+ str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l);
fprintf(f, "%s\n", str.c_str());
}
if(output_width < w && (cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos"))
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
++line_num;
- std::string op = cell_type_translation.at(cell->type);
+ std::string op = cell_type_translation.at(cell->type.str());
if(cell->type == "$lt" || cell->type == "$le" ||
cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
cell->type == "$ge" || cell->type == "$gt")
{
if(l1_signed)
- op = s_cell_type_translation.at(cell->type);
+ op = s_cell_type_translation.at(cell->type.str());
}
str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
++line_num;
- std::string op = cell_type_translation.at(cell->type);
+ std::string op = cell_type_translation.at(cell->type.str());
if(cell->type == "$div" && l1_signed)
- op = s_cell_type_translation.at(cell->type);
+ op = s_cell_type_translation.at(cell->type.str());
else if(cell->type == "$mod")
{
if(l1_signed)
int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
int cell_output = ++line_num;
- str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
+ str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
fprintf(f, "%s\n", str.c_str());
if(l2_width > ceil(log(l1_width)/log(2)))
int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
++line_num;
str = stringf ("%d %s %d %d %d %d",
- line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
+ line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
fprintf(f, "%s\n", str.c_str());
line_ref[cell->name]=line_num;
}
fprintf(f, "%s\n", str.c_str());
}
++line_num;
- str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(),
+ str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(),
output_width, reg, next);
fprintf(f, "%s\n", str.c_str());
}
log_assert(output->size() == output_width);
int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
++line_num;
- str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);
+ str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset);
fprintf(f, "%s\n", str.c_str());
line_ref[cell->name]=line_num;
}
log_assert(input_b->size() == input_b_width);
int input_b_line = dump_sigspec(input_b, input_b_width);
++line_num;
- str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width,
+ str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width,
input_a_line, input_b_line);
fprintf(f, "%s\n", str.c_str());
line_ref[cell->name]=line_num;
inputs[wire->port_id] = wire;
if (wire->port_output) {
outputs[wire->port_id] = wire;
- if (wire->name.find("safety") != std::string::npos )
+ if (wire->name.str().find("safety") != std::string::npos )
safety.push_back(wire);
}
}
log_header("Executing EDIF backend.\n");
std::string top_module_name;
- std::map<std::string, std::set<std::string>> lib_cell_ports;
+ std::map<RTLIL::IdString, std::set<RTLIL::IdString>> lib_cell_ports;
CellTypes ct(design);
EdifNames edif_names;
bool norename, noattr, attr2comment, noexpr;
int auto_name_counter, auto_name_offset, auto_name_digits;
-std::map<std::string, int> auto_name_map;
+std::map<RTLIL::IdString, int> auto_name_map;
-std::set<std::string> reg_wires;
+std::set<RTLIL::IdString> reg_wires;
CellTypes reg_ct;
RTLIL::Module *active_module;
-void reset_auto_counter_id(const std::string &id, bool may_rename)
+void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
{
const char *str = id.c_str();
log(" renaming `%s' to `_%0*d_'.\n", it->first.c_str(), auto_name_digits, auto_name_offset + it->second);
}
-std::string id(std::string internal_id, bool may_rename = true)
+std::string id(RTLIL::IdString internal_id, bool may_rename = true)
{
const char *str = internal_id.c_str();
bool do_escape = false;
if (wire->name[0] != '\\')
goto no_special_reg_name;
- std::string cell_name = wire->name;
+ std::string cell_name = wire->name.str();
size_t pos = cell_name.find('[');
if (pos != std::string::npos)
fprintf(f, " %s (", cell_name.c_str());
bool first_arg = true;
- std::set<std::string> numbered_ports;
+ std::set<RTLIL::IdString> numbered_ports;
for (int i = 1; true; i++) {
char str[16];
snprintf(str, 16, "$%d", i);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
+ RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
if (gen_attributes)
RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", width);
+ RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
if (that != NULL)
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
+ RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
for (auto &attr : that->attributes) {
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", left.size());
+ RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
for (auto &attr : that->attributes) {
do {
wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
- if (chunk.wire->name.find('$') != std::string::npos)
+ if (chunk.wire->name.str().find('$') != std::string::npos)
wire_name += stringf("$%d", autoidx++);
} while (current_module->wires_.count(wire_name) > 0);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- RTLIL::Wire *wire = current_module->addWire(cell->name + "_DATA", current_module->memories[str]->width);
+ RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
int addr_bits = 1;
for (auto &v : c.data.bits)
DJB2(that->hash_, v);
} else {
- for (auto &v : c.wire->name)
+ for (auto &v : c.wire->name.str())
DJB2(that->hash_, v);
DJB2(that->hash_, c.offset);
DJB2(that->hash_, c.width);
typedef std::pair<SigSpec, SigSpec> SigSig;
-#if 1
- struct IdString : public std::string {
- IdString() { }
- IdString(std::string str) : std::string(str) {
- check();
- }
- IdString(const char *s) : std::string(s) {
- check();
- }
- IdString &operator=(const std::string &str) {
- std::string::operator=(str);
- check();
- return *this;
- }
- IdString &operator=(const char *s) {
- std::string::operator=(s);
- check();
- return *this;
- }
- bool operator<(const IdString &rhs) {
- check(), rhs.check();
- return std::string(*this) < std::string(rhs);
- }
- void check() const {
- log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
- }
- const std::string& str() const {
- return *this;
- }
- };
-#else
- struct IdString {
- IdString();
- IdString(const char *str);
- IdString(const IdString &str);
- IdString(const std::string &str);
-
- void operator=(const char *rhs);
- void operator=(const IdString &rhs);
- void operator=(const std::string &rhs);
-
- operator const char*() const;
- const std::string& str() const;
-
- bool operator<(const IdString &rhs) const;
- bool operator==(const IdString &rhs) const;
- bool operator!=(const IdString &rhs) const;
- bool operator==(const char *rhs) const;
- bool operator!=(const char *rhs) const;
- std::string operator+(const char *other) const;
-
- std::string::const_iterator begin() const;
- std::string::const_iterator end() const;
- char at(int i) const;
- const char*c_str() const;
- size_t find(char c) const;
- std::string substr(size_t pos = 0, size_t len = std::string::npos) const;
- size_t size() const;
- bool empty() const;
- void clear();
+ struct IdString
+ {
+ private:
+ std::string str_;
+
+ public:
+ IdString() : str_() { }
+ IdString(const char *str) : str_(str) { }
+ IdString(const IdString &str) : str_(str.str_) { }
+ IdString(const std::string &str) : str_(str) { }
+
+ void operator=(const char *rhs) { str_ = rhs; }
+ void operator=(const IdString &rhs) { str_ = rhs.str_; }
+ void operator=(const std::string &rhs) { str_ = rhs; }
+
+ const std::string& str() const { return str_; }
+
+ // The methods below are just convinience functions for better compatibility
+ // with std::string. Except clear() they all just deligate to std::string.
+
+ operator const char*() const { return str().c_str(); }
+
+ bool operator<(const IdString &rhs) const { return str() < rhs.str(); }
+ bool operator==(const IdString &rhs) const { return str() == rhs.str(); }
+ bool operator!=(const IdString &rhs) const { return str() != rhs.str(); }
+
+ bool operator==(const char *rhs) const { return str() == rhs; }
+ bool operator!=(const char *rhs) const { return str() != rhs; }
+
+ char at(size_t i) const { return str().at(i); }
+ const char*c_str() const { return str().c_str(); }
+ std::string substr(size_t pos = 0, size_t len = std::string::npos) const { return str().substr(pos, len); }
+ size_t size() const { return str().size(); }
+ bool empty() const { return str().empty(); }
+ void clear() { *this = IdString(); }
};
-#endif
-
static inline std::string escape_id(std::string str) {
if (str.size() > 0 && str[0] != '\\' && str[0] != '$')
return "\\" + str;
bool is_signed;
};
- std::set<std::string> decl_celltypes;
- std::map<std::pair<std::string, std::string>, portdecl_t> decls;
+ std::set<RTLIL::IdString> decl_celltypes;
+ std::map<std::pair<RTLIL::IdString, RTLIL::IdString>, portdecl_t> decls;
void add_port(std::string celltype, std::string portname, std::string widthparam, std::string signparam)
{
for (auto &conn : cell->connections())
{
- std::pair<std::string, std::string> key(cell->type, conn.first);
+ std::pair<RTLIL::IdString, RTLIL::IdString> key(cell->type, conn.first);
if (!decls.count(key))
continue;
return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits);
}
- const char *findColor(std::string member_name)
+ const char *findColor(RTLIL::IdString member_name)
{
for (auto &s : color_selections)
if (s.second.selected_member(module->name, member_name)) {
return "";
}
- const char *findLabel(std::string member_name)
+ const char *findLabel(RTLIL::IdString member_name)
{
for (auto &s : label_selections)
- if (s.second.selected_member(module->name, RTLIL::escape_id(member_name)))
+ if (s.second.selected_member(module->name, member_name))
return escape(s.first);
return escape(member_name, true);
}
- const char *escape(std::string id, bool is_name = false)
+ const char *escape(RTLIL::IdString id, bool is_name = false)
{
- if (id.size() == 0)
+ std::string id_str = id.str();
+
+ if (id_str.size() == 0)
return "";
- if (id[0] == '$' && is_name) {
+ if (id_str[0] == '$' && is_name) {
if (enumerateIds) {
if (autonames.count(id) == 0) {
autonames[id] = autonames.size() + 1;
}
id = stringf("_%d_", autonames[id]);
} else if (abbreviateIds) {
- const char *p = id.c_str();
+ const char *p = id_str.c_str();
const char *q = strrchr(p, '$');
- id = std::string(q);
+ id_str = std::string(q);
}
}
- if (id[0] == '\\')
- id = id.substr(1);
+ if (id_str[0] == '\\')
+ id_str = id_str.substr(1);
std::string str;
- for (char ch : id) {
+ for (char ch : id_str) {
if (ch == '\\' || ch == '"')
str += "\\";
str += ch;
bool sel_by_wire;
bool sel_any_bit;
bool no_outputs;
- std::set<std::string> ports;
- std::set<std::string> no_ports;
+ std::set<RTLIL::IdString> ports;
+ std::set<RTLIL::IdString> no_ports;
CellTypes ct;
SigMap sigmap;
for (auto &it : rework_wires)
{
- std::string orig_name = it.first->name;
+ RTLIL::IdString orig_name = it.first->name;
module->rename(it.first, NEW_ID);
RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
bool sel_by_wire = false;
bool sel_any_bit = false;
bool no_outputs = false;
- std::set<std::string> ports, no_ports;
+ std::set<RTLIL::IdString> ports, no_ports;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
{
- std::string new_wire_name = wire->name;
+ std::string new_wire_name = wire->name.str();
if (format.size() > 0)
new_wire_name += format.substr(0, 1);
static RTLIL::Module *module;
static SigMap assign_map;
-typedef std::pair<RTLIL::Cell*,std::string> sig2driver_entry_t;
+typedef std::pair<RTLIL::Cell*, RTLIL::IdString> sig2driver_entry_t;
static SigSet<sig2driver_entry_t> sig2driver, sig2user;
static std::set<RTLIL::Cell*> muxtree_cells;
static SigPool sig_at_port;
}
else {
kiss_name.assign(module->name);
- kiss_name.append('-' + cell->name + ".kiss2");
+ kiss_name.append('-' + cell->name.str() + ".kiss2");
}
log("\n");
static RTLIL::Module *module;
static SigMap assign_map;
-typedef std::pair<std::string, std::string> sig2driver_entry_t;
+typedef std::pair<RTLIL::IdString, RTLIL::IdString> sig2driver_entry_t;
static SigSet<sig2driver_entry_t> sig2driver, sig2trigger;
static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
fsm_cell->setPort("\\CTRL_IN", ctrl_in);
fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
- fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
+ fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes;
fsm_data.copy_to_cell(fsm_cell);
static void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
{
- std::set<std::string> found_celltypes;
+ std::set<RTLIL::IdString> found_celltypes;
for (auto i1 : design->modules_)
for (auto i2 : i1.second->cells_)
for (auto &celltype : found_celltypes)
{
- std::set<std::string> portnames;
- std::set<std::string> parameters;
- std::map<std::string, int> portwidths;
+ std::set<RTLIL::IdString> portnames;
+ std::set<RTLIL::IdString> parameters;
+ std::map<RTLIL::IdString, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
for (auto i1 : design->modules_)
}
while (portnames.size() > 0) {
- std::string portname = *portnames.begin();
+ RTLIL::IdString portname = *portnames.begin();
for (auto &decl : portdecls)
if (decl.index == 0 && !fnmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str(), FNM_NOESCAPE)) {
generate_port_decl_t d = decl;
RTLIL::Cell *cell = cell_it.second;
if (cell->type.substr(0, 7) == "$array:") {
- int pos_idx = cell->type.find_first_of(':');
- int pos_num = cell->type.find_first_of(':', pos_idx + 1);
- int pos_type = cell->type.find_first_of(':', pos_num + 1);
- int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str());
- int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str());
+ int pos_idx = cell->type.str().find_first_of(':');
+ int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
+ int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
+ int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
+ int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
array_cells[cell] = std::pair<int, int>(idx, num);
- cell->type = cell->type.substr(pos_type + 1);
+ cell->type = cell->type.str().substr(pos_type + 1);
}
if (design->modules_.count(cell->type) == 0)
{
- if (design->modules_.count("$abstract" + cell->type))
+ if (design->modules_.count("$abstract" + cell->type.str()))
{
- cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters);
+ cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
cell->parameters.clear();
did_something = true;
continue;
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
- std::string portname = conn.first;
+ RTLIL::IdString portname = conn.first;
if (portname.substr(0, 1) == "$") {
int port_id = atoi(portname.substr(1).c_str());
for (auto &wire_it : mod->wires_)
bool did_something_once = false;
while (did_something) {
did_something = false;
- std::vector<std::string> modnames;
+ std::vector<RTLIL::IdString> modnames;
modnames.reserve(design->modules_.size());
for (auto &mod_it : design->modules_)
modnames.push_back(mod_it.first);
design->add(new_mod);
int port_counter = 1, auto_name_counter = 1;
- std::set<std::string> all_wire_names;
+ std::set<RTLIL::IdString> all_wire_names;
for (auto &it : wire_flags) {
all_wire_names.insert(it.first->name);
}
if (flags.is_int_driven && flags.is_ext_driven)
new_wire_port_input = true, new_wire_port_output = true;
- std::string new_wire_name = wire->name;
+ std::string new_wire_name = wire->name.str();
if (new_wire_port_input || new_wire_port_output) {
while (new_wire_name[0] == '$') {
std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
if (submodules.count(submod_str) == 0) {
submodules[submod_str].name = submod_str;
- submodules[submod_str].full_name = module->name + "_" + submod_str;
+ submodules[submod_str].full_name = module->name.str() + "_" + submod_str;
while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
module->count_id(submodules[submod_str].full_name) != 0)
submodules[submod_str].full_name += "_";
Pass::call(design, "opt_clean");
log_header("Continuing SUBMOD pass.\n");
- std::set<std::string> handled_modules;
+ std::set<RTLIL::IdString> handled_modules;
bool did_something = true;
while (did_something) {
did_something = false;
- std::vector<std::string> queued_modules;
+ std::vector<RTLIL::IdString> queued_modules;
for (auto &mod_it : design->modules_)
if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
queued_modules.push_back(mod_it.first);
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name)
+ if ((cell->type == "$memwr" || cell->type == "$memrd") && memory->name == cell->parameters["\\MEMID"].decode_string())
memcells.push_back(cell);
}
for (auto cell : memcells)
{
- if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
+ if (cell->type == "$memwr" && memory->name == cell->parameters["\\MEMID"].decode_string())
{
wr_ports++;
del_cells.push_back(cell);
sig_wr_en.append(en);
}
- if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name)
+ if (cell->type == "$memrd" && memory->name == cell->parameters["\\MEMID"].decode_string())
{
rd_ports++;
del_cells.push_back(cell);
sstr << "$mem$" << memory->name << "$" << (autoidx++);
RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
- mem->parameters["\\MEMID"] = RTLIL::Const(memory->name);
+ mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());
mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width);
mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset);
mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
#include <set>
#include <stdlib.h>
-static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
+static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
{
std::stringstream sstr;
- sstr << "$memory" << name << token1;
+ sstr << "$memory" << name.str() << token1;
if (i >= 0)
sstr << "[" << i << "]";
RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
while (module->memories.count(mem_name) != 0)
- mem_name += stringf("_%d", autoidx++);
+ mem_name = mem_name.str() + stringf("_%d", autoidx++);
RTLIL::Memory *mem = new RTLIL::Memory;
mem->name = mem_name;
for (int i = 0; i < num_rd_ports; i++)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
- cell->parameters["\\MEMID"] = mem_name;
+ cell->parameters["\\MEMID"] = mem_name.str();
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
for (int i = 0; i < num_wr_ports; i++)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
- cell->parameters["\\MEMID"] = mem_name;
+ cell->parameters["\\MEMID"] = mem_name.str();
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
static bool check_public_name(RTLIL::IdString id)
{
- if (id[0] == '$')
+ const std::string &id_str = id.str();
+ if (id_str[0] == '$')
return false;
- if (id.substr(0, 2) == "\\_" && (id[id.size()-1] == '_' || id.find("_[") != std::string::npos))
+ if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos))
return false;
- if (id.find(".$") != std::string::npos)
+ if (id_str.find(".$") != std::string::npos)
return false;
return true;
}
log("\n");
}
- cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type);
+ cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str());
module->remove(cell);
OPT_DID_SOMETHING = true;
}
if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
- cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
+ cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str());
log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort("\\A", sig_a = new_a);
}
if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) {
- cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
+ cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type.str());
log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort("\\B", sig_b = new_b);
if (0) {
found_the_x_bit:
cover_list("opt.opt_const.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
- "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type);
+ "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str());
if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" ||
cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 &&
invert_map.count(assign_map(cell->getPort("\\A"))) != 0) {
- cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type);
+ cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type.str());
replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A"))));
goto next_cell;
}
if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
- cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type);
+ cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
RTLIL::SigSpec tmp = cell->getPort("\\A");
cell->setPort("\\A", cell->getPort("\\B"));
cell->setPort("\\B", tmp);
log_assert(SIZE(a) == SIZE(b));
for (int i = 0; i < SIZE(a); i++) {
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
- cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type);
+ cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y);
}
if (new_a.size() == 0) {
- cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type);
+ cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(assign_map, module, cell, "empty", "\\Y", new_y);
}
if (new_a.size() < a.size() || new_b.size() < b.size()) {
- cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type);
+ cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
cell->setPort("\\A", new_a);
cell->setPort("\\B", new_b);
cell->parameters["\\A_WIDTH"] = new_a.size();
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (a.is_fully_const()) {
- cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
+ cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type.str());
RTLIL::SigSpec tmp = cell->getPort("\\A");
cell->setPort("\\A", cell->getPort("\\B"));
cell->setPort("\\B", tmp);
RTLIL::SigSpec input = b;
ACTION_DO("\\Y", cell->getPort("\\A"));
} else {
- cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type);
+ cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type.str());
cell->type = "$not";
cell->parameters.erase("\\B_WIDTH");
cell->parameters.erase("\\B_SIGNED");
if (identity_wrt_a || identity_wrt_b)
{
if (identity_wrt_a)
- cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type);
+ cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
if (identity_wrt_b)
- cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type);
+ cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
- cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type);
+ cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type.str());
replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S"));
goto next_cell;
}
if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) {
- cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
+ cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type.str());
cell->setPort("\\A", cell->getPort("\\S"));
cell->unsetPort("\\B");
cell->unsetPort("\\S");
}
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
- cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
+ cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type.str());
cell->setPort("\\A", cell->getPort("\\S"));
cell->unsetPort("\\S");
if (cell->type == "$mux") {
}
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
- cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
+ cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type.str());
cell->setPort("\\B", cell->getPort("\\S"));
cell->unsetPort("\\S");
if (cell->type == "$mux") {
int width = cell->getPort("\\A").size();
if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) ||
cell->getPort("\\S").is_fully_undef()) {
- cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type);
+ cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A"));
goto next_cell;
}
new_s = new_s.extract(0, new_s.size()-1);
}
if (new_s.size() == 0) {
- cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type);
+ cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_empty", "\\Y", new_a);
goto next_cell;
}
if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) {
- cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type);
+ cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s);
goto next_cell;
}
if (cell->getPort("\\S").size() != new_s.size()) {
- cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
+ cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type.str());
cell->setPort("\\A", new_a);
cell->setPort("\\B", new_b);
cell->setPort("\\S", new_s);
dff_init_map.add(it.second, it.second->attributes.at("\\init"));
mux_drivers.clear();
- std::vector<std::string> dff_list;
+ std::vector<RTLIL::IdString> dff_list;
for (auto &it : mod_it.second->cells_) {
if (it.second->type == "$mux" || it.second->type == "$pmux") {
if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size())
if (cell_hash_cache.count(cell) > 0)
return cell_hash_cache[cell];
- std::string hash_string = cell->type + "\n";
+ std::string hash_string = cell->type.str() + "\n";
for (auto &it : cell->parameters)
- hash_string += "P " + it.first + "=" + it.second.as_string() + "\n";
+ hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
continue;
RTLIL::SigSpec sig = it.second;
assign_map.apply(sig);
- hash_string += "C " + it.first + "=";
+ hash_string += "C " + it.first.str() + "=";
for (auto &chunk : sig.chunks()) {
if (chunk.wire)
- hash_string += "{" + chunk.wire->name + " " +
+ hash_string += "{" + chunk.wire->name.str() + " " +
int_to_hash_string(chunk.offset) + " " +
int_to_hash_string(chunk.width) + "}";
else
extra_args(args, 1, design);
for (auto mod : design->modules()) {
- std::vector<std::string> delme;
+ std::vector<RTLIL::IdString> delme;
if (!design->selected(mod))
continue;
for (auto &proc_it : mod->processes) {
if (shows.size() == 0) {
for (auto &it : module->wires_)
if (it.second->port_output)
- shows.push_back(it.second->name);
+ shows.push_back(it.second->name.str());
}
if (tables.empty())
RTLIL::SigSpec sig_d, sig_clk, sig_arst;
bool clk_polarity, arst_polarity;
RTLIL::Const arst_value;
- std::vector<std::string> cells;
+ std::vector<RTLIL::IdString> cells;
};
struct dff_map_bit_info_t {
RTLIL::Cell *cell;
};
-static bool consider_wire(RTLIL::Wire *wire, std::map<std::string, dff_map_info_t> &dff_dq_map)
+static bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
{
if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
return false;
return true;
}
-static bool consider_cell(RTLIL::Design *design, std::set<std::string> &dff_cells, RTLIL::Cell *cell)
+static bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells, RTLIL::Cell *cell)
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false;
return true;
}
-static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *module)
+static void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
{
CellTypes ct;
ct.setup_internals_mem();
}
}
-static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
+static void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
{
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
}
}
- std::map<std::string, dff_map_info_t> empty_dq_map;
+ std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
for (auto &it : module->wires_)
{
if (!consider_wire(it.second, empty_dq_map))
}
}
-static RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1)
+static RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
{
if (module->count_id(name))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
CellTypes ct(design);
- std::map<RTLIL::Module*, std::map<std::string, dff_map_info_t>> dff_dq_maps;
- std::map<RTLIL::Module*, std::set<std::string>> dff_cells;
+ std::map<RTLIL::Module*, std::map<RTLIL::IdString, dff_map_info_t>> dff_dq_maps;
+ std::map<RTLIL::Module*, std::set<RTLIL::IdString>> dff_cells;
if (flag_evert_dff)
{
RTLIL::Module *first_module = NULL;
- std::set<std::string> shared_dff_wires;
+ std::set<RTLIL::IdString> shared_dff_wires;
for (auto &mod_it : design->modules_)
{
shared_dff_wires.insert(it.first);
first_module = mod_it.second;
} else {
- std::set<std::string> new_shared_dff_wires;
+ std::set<RTLIL::IdString> new_shared_dff_wires;
for (auto &it : shared_dff_wires) {
if (!dff_dq_maps[mod_it.second].count(it))
continue;
if (flag_shared)
for (auto &map_it : dff_dq_maps)
{
- std::map<std::string, dff_map_info_t> new_map;
+ std::map<RTLIL::IdString, dff_map_info_t> new_map;
for (auto &it : map_it.second)
if (shared_dff_wires.count(it.first))
new_map[it.first] = it.second;
dff_cells[it1.first].insert(it3);
}
- std::set<std::string> shared_wires, shared_cells;
- std::set<std::string> used_names;
+ std::set<RTLIL::IdString> shared_wires, shared_cells;
+ std::set<RTLIL::IdString> used_names;
if (flag_shared)
{
if (!design->selected(module))
continue;
- std::set<std::string> dff_wires;
+ std::set<RTLIL::IdString> dff_wires;
if (flag_dff)
find_dff_wires(dff_wires, module);
}
else
{
- std::vector<std::string> delete_shared_wires, delete_shared_cells;
+ std::vector<RTLIL::IdString> delete_shared_wires, delete_shared_cells;
for (auto &it : shared_wires)
{
if (!design->selected(module))
continue;
- std::set<std::string> dff_wires;
+ std::set<RTLIL::IdString> dff_wires;
if (flag_dff && !flag_shared)
find_dff_wires(dff_wires, module);
}
if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, it.second->name + sep + "i", it.second->width);
+ RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width);
in_wire->port_input = true;
out_to_in_map.add(sigmap(it.second), in_wire);
}
cell->setPort("\\Q", cell_q_bits);
}
- RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width);
+ RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
wire_q->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
}
module->connect(connect_q);
- RTLIL::Wire *wire_d = add_new_wire(module, wire->name + sep + "d", wire->width);
+ RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width);
wire_d->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
module->connect(RTLIL::SigSig(wire_d, info.sig_d));
- RTLIL::Wire *wire_c = add_new_wire(module, wire->name + sep + "c");
+ RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c");
wire_c->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
if (info.clk_polarity) {
if (info.sig_arst != RTLIL::State::Sm)
{
- RTLIL::Wire *wire_r = add_new_wire(module, wire->name + sep + "r");
+ RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r");
wire_r->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
if (info.arst_polarity) {
c->setPort("\\Y", wire_r);
}
- RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width);
+ RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
wire_v->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
module->connect(RTLIL::SigSig(wire_v, info.arst_value));
if (!p->port_input && !p->port_output)
continue;
- RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(p->name), p->width);
+ RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(p->name), p->width);
if (p->port_input)
w->port_output = true;
if (p->port_output)
{
for (auto &it : cell->connections())
{
- RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(it.first), it.second.size());
+ RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(it.first), it.second.size());
if (ct.cell_input(cell->type, it.first))
w->port_output = true;
if (ct.cell_output(cell->type, it.first))
if (set_def_inputs) {
for (auto &it : module->wires_)
if (it.second->port_input)
- sets_def.push_back(it.second->name);
+ sets_def.push_back(it.second->name.str());
}
if (show_inputs) {
for (auto &it : module->wires_)
if (it.second->port_input)
- shows.push_back(it.second->name);
+ shows.push_back(it.second->name.str());
}
if (show_outputs) {
for (auto &it : module->wires_)
if (it.second->port_output)
- shows.push_back(it.second->name);
+ shows.push_back(it.second->name.str());
}
if (tempinduct)
bool opt_force;
bool opt_aggressive;
bool opt_fast;
- std::set<std::string> generic_uni_ops, generic_bin_ops, generic_cbin_ops;
+ std::set<RTLIL::IdString> generic_uni_ops, generic_bin_ops, generic_cbin_ops;
};
struct ShareWorker
{
ShareWorkerConfig config;
- std::set<std::string> generic_ops;
+ std::set<RTLIL::IdString> generic_ops;
RTLIL::Design *design;
RTLIL::Module *module;
std::string cell_name;
std::map<std::string, char> ports;
};
-static std::map<std::string, cell_mapping> cell_mappings;
+static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
static void logmap(std::string dff)
{
bool return_status = false;
for (auto &it : cell_mappings) {
- std::string from = it.first, to = it.first;
+ std::string from = it.first.str(), to = it.first.str();
if (from.size() != pattern.size())
continue;
for (size_t i = 0; i < from.size(); i++) {
{
public:
bool ignore_parameters;
- std::set<std::pair<std::string, std::string>> ignored_parameters;
+ std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> ignored_parameters;
std::set<RTLIL::IdString> cell_attr, wire_attr;
SubCircuitSolver() : ignore_parameters(false)
if (!ignore_parameters) {
std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
for (auto &it : needleCell->parameters)
- if (!ignored_parameters.count(std::pair<std::string, std::string>(needleCell->type, it.first)))
+ if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
for (auto &it : haystackCell->parameters)
- if (!ignored_parameters.count(std::pair<std::string, std::string>(haystackCell->type, it.first)))
+ if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
if (needle_param != haystack_param)
return false;
for (auto &conn : needleCell->connections())
{
RTLIL::SigSpec needleSig = conn.second;
- RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first));
+ RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
if (sel && !sel->selected(mod, cell))
continue;
- std::string type = cell->type;
+ std::string type = cell->type.str();
if (sel == NULL && type.substr(0, 2) == "\\$")
type = type.substr(1);
- graph.createNode(cell->name, type, (void*)cell);
+ graph.createNode(cell->name.str(), type, (void*)cell);
for (auto &conn : cell->connections())
{
- graph.createPort(cell->name, conn.first, conn.second.size());
+ graph.createPort(cell->name.str(), conn.first.str(), conn.second.size());
if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
continue;
if (bit == RTLIL::State::S0) node = "$const$0";
if (bit == RTLIL::State::S1) node = "$const$1";
if (bit == RTLIL::State::Sz) node = "$const$z";
- graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0);
+ graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
} else
- graph.createConstant(cell->name, conn.first, i, int(bit.data));
+ graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
continue;
}
}
bit_ref_t &bit_ref = sig_bit_ref[bit];
- graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i);
+ graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
}
}
}
RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
{
SigMap sigmap(needle);
- SigSet<std::pair<std::string, int>> sig2port;
+ SigSet<std::pair<RTLIL::IdString, int>> sig2port;
// create new cell
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
- sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
+ sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
}
}
for (auto &conn : needle_cell->connections()) {
RTLIL::SigSpec sig = sigmap(conn.second);
- if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
+ if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) {
for (int i = 0; i < sig.size(); i++)
for (auto &port : sig2port.find(sig[i])) {
- RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first]).extract(i, 1);
+ RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1);
RTLIL::SigSpec new_sig = cell->getPort(port.first);
new_sig.replace(port.second, bitsig);
cell->setPort(port.first, new_sig);
continue;
}
if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) {
- solver.ignored_parameters.insert(std::pair<std::string, std::string>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
+ solver.ignored_parameters.insert(std::pair<RTLIL::IdString, RTLIL::IdString>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
argidx += 2;
continue;
}
#include <stdio.h>
#include <string.h>
-extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
}
}
-void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
+void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
mappers["$not"] = simplemap_not;
mappers["$pos"] = simplemap_pos;
log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
extra_args(args, 1, design);
- std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
+ std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);
for (auto mod : design->modules()) {
#include "passes/techmap/techmap.inc"
// see simplemap.cc
-extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
static void apply_prefix(std::string prefix, std::string &id)
{
std::vector<RTLIL::SigChunk> chunks = sig;
for (auto &chunk : chunks)
if (chunk.wire != NULL) {
- std::string wire_name = chunk.wire->name;
+ std::string wire_name = chunk.wire->name.str();
apply_prefix(prefix, wire_name);
log_assert(module->wires_.count(wire_name) > 0);
chunk.wire = module->wires_[wire_name];
struct TechmapWorker
{
- std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
+ std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
std::map<RTLIL::Module*, bool> techmap_do_cache;
std::set<RTLIL::Module*> module_queue;
std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
{
std::string constmap_info;
- std::map<RTLIL::SigBit, std::pair<std::string, int>> connbits_map;
+ std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
for (auto conn : cell->connections())
for (int i = 0; i < SIZE(conn.second); i++) {
constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
} else
- connbits_map[bit] = std::pair<std::string, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data);
+ connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data);
}
return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
- module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name);
+ module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
}
for (auto &it : tpl->wires_) {
if (it.second->port_id > 0)
positional_ports[stringf("$%d", it.second->port_id)] = it.first;
- std::string w_name = it.second->name;
- apply_prefix(cell->name, w_name);
+ std::string w_name = it.second->name.str();
+ apply_prefix(cell->name.str(), w_name);
RTLIL::Wire *w = module->addWire(w_name, it.second);
w->port_input = false;
w->port_output = false;
if (w->port_output) {
c.first = it.second;
c.second = RTLIL::SigSpec(w);
- apply_prefix(cell->name, c.second, module);
+ apply_prefix(cell->name.str(), c.second, module);
} else {
c.first = RTLIL::SigSpec(w);
c.second = it.second;
- apply_prefix(cell->name, c.first, module);
+ apply_prefix(cell->name.str(), c.first, module);
}
if (c.second.size() > c.first.size())
c.second.remove(c.first.size(), c.second.size() - c.first.size());
for (auto &it : tpl->cells_)
{
- RTLIL::IdString c_name = it.second->name;
+ std::string c_name = it.second->name.str();
if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
c_name = orig_cell_name;
else
- apply_prefix(cell->name, c_name);
+ apply_prefix(cell->name.str(), c_name);
RTLIL::Cell *c = module->addCell(c_name, it.second);
design->select(module, c);
c->type = c->type.substr(1);
for (auto &it2 : c->connections_) {
- apply_prefix(cell->name, it2.second, module);
+ apply_prefix(cell->name.str(), it2.second, module);
port_signal_map.apply(it2.second);
}
}
for (auto &it : tpl->connections()) {
RTLIL::SigSig c = it;
- apply_prefix(cell->name, c.first, module);
- apply_prefix(cell->name, c.second, module);
+ apply_prefix(cell->name.str(), c.first, module);
+ apply_prefix(cell->name.str(), c.second, module);
port_signal_map.apply(c.first);
port_signal_map.apply(c.second);
module->connect(c);
continue;
if (celltypeMap.count(cell->type) == 0) {
- if (assert_mode && cell->type.back() != '_')
+ if (assert_mode && cell->type.str().back() != '_')
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
continue;
}
for (auto &tpl_name : celltypeMap.at(cell->type))
{
- std::string derived_name = tpl_name;
+ RTLIL::IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->modules_[tpl_name];
std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
if (!wire->port_input || wire->port_output)
continue;
- std::string port_name = wire->name;
+ RTLIL::IdString port_name = wire->name;
tpl->rename(wire, NEW_ID);
RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
RTLIL::Wire *wire = it2->second;
if (wire->port_output) {
count_ports++;
- signal_out[idy("sig", mod->name, wire->name)] = wire->width;
- fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
+ signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
+ fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
} else if (wire->port_input) {
count_ports++;
bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
is_clksignal = true;
}
if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
- signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
+ signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
} else {
- signal_in[idy("sig", mod->name, wire->name)] = wire->width;
+ signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
if (wire->attributes.count("\\gentb_constant") != 0)
- signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
+ signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string();
}
- fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
+ fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
}
}
- fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str());
+ fprintf(f, "%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) {
RTLIL::Wire *wire = it2->second;
if (wire->port_output || wire->port_input)
- fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(),
- idy("sig", mod->name, wire->name).c_str(), --count_ports ? "," : "");
+ fprintf(f, "\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
+ idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : "");
}
fprintf(f, ");\n\n");
- fprintf(f, "task %s;\n", idy(mod->name, "reset").c_str());
+ fprintf(f, "task %s;\n", idy(mod->name.str(), "reset").c_str());
fprintf(f, "begin\n");
int delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); it++)
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
- fprintf(f, "task %s;\n", idy(mod->name, "update_data").c_str());
+ fprintf(f, "task %s;\n", idy(mod->name.str(), "update_data").c_str());
fprintf(f, "begin\n");
delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
- fprintf(f, "task %s;\n", idy(mod->name, "update_clock").c_str());
+ fprintf(f, "task %s;\n", idy(mod->name.str(), "update_clock").c_str());
fprintf(f, "begin\n");
if (signal_clk.size()) {
fprintf(f, "\txorshift128;\n");
std::vector<std::string> header1;
std::string header2 = "";
- fprintf(f, "task %s;\n", idy(mod->name, "print_status").c_str());
+ fprintf(f, "task %s;\n", idy(mod->name.str(), "print_status").c_str());
fprintf(f, "begin\n");
fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {");
if (signal_in.size())
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
- fprintf(f, "task %s;\n", idy(mod->name, "print_header").c_str());
+ fprintf(f, "task %s;\n", idy(mod->name.str(), "print_header").c_str());
fprintf(f, "begin\n");
fprintf(f, "\t$display(\"#OUT#\");\n");
for (auto &hdr : header1)
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
- fprintf(f, "task %s;\n", idy(mod->name, "test").c_str());
+ fprintf(f, "task %s;\n", idy(mod->name.str(), "test").c_str());
fprintf(f, "begin\n");
- fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str());
- fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str());
+ fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
+ fprintf(f, "\t%s;\n", idy(mod->name.str(), "reset").c_str());
fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
- fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str());
- fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_data").c_str());
- fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_clock").c_str());
- fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "print_status").c_str());
+ fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
+ fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
+ fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
+ fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
fprintf(f, "\tend\n");
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
fprintf(f, "\t// $dumpvars(0, testbench);\n");
for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
if (!it->second->get_bool_attribute("\\gentb_skip"))
- fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
+ fprintf(f, "\t%s;\n", idy(it->first.str(), "test").c_str());
fprintf(f, "\t$finish;\n");
fprintf(f, "end\n\n");
projects / yosys.git / commitdiff