Added synthesis target

The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1

diff --git a/microwatt.core b/microwatt.core
index 30354ce986a3d2888ee525aba5214e16e02f9f43..1abc5584e0e2ffa92dad838b0c494839aa018d1d 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -66,6 +66,12 @@ targets:
       vivado: {part : xc7a200tsbg484-1}
     toplevel : toplevel
 
+  synth:
+    filesets: [core]
+    tools:
+      vivado: {pnr : none}
+    toplevel: core
+
 parameters:
   memory_size:
     datatype    : int