Using $pos models for $bu0

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d1fa55b9450d5ebb02f3ae3a4ea2f6a71a3b2aac..79672540b2ca42e84275df345b984c1262fcf4fc 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -538,6 +538,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
        HANDLE_UNIOP("$not", "~")
        HANDLE_UNIOP("$pos", "+")
+       HANDLE_UNIOP("$bu0", "+")
        HANDLE_UNIOP("$neg", "-")
 
        HANDLE_BINOP("$and",  "&")
@@ -651,22 +652,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
                return true;
        }
 
-       if (cell->type == "$bu0")
-       {
-               f << stringf("%s" "assign ", indent.c_str());
-               dump_sigspec(f, cell->getPort("\\Y"));
-               if (cell->parameters["\\A_SIGNED"].as_bool()) {
-                       f << stringf(" = $signed(");
-                       dump_sigspec(f, cell->getPort("\\A"));
-                       f << stringf(");\n");
-               } else {
-                       f << stringf(" = { 1'b0, ");
-                       dump_sigspec(f, cell->getPort("\\A"));
-                       f << stringf(" };\n");
-               }
-               return true;
-       }
-
        if (cell->type == "$concat")
        {
                f << stringf("%s" "assign ", indent.c_str());

diff --git a/kernel/calc.cc b/kernel/calc.cc
index 4048e4a1f0f884a3dfdf6766054928b204f6f8cf..da03f61642b131b8557d66485627514d3ed74da7 100644 (file)
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -575,7 +575,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
 RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
 {
        RTLIL::Const arg1_ext = arg1;
-       extend(arg1_ext, result_len, signed1);
+       extend_u0(arg1_ext, result_len, signed1);
 
        return arg1_ext;
 }

diff --git a/kernel/satgen.h b/kernel/satgen.h
index c7f1680d4c31da70c11c31157d306aaec6e7c7dc..eed3adaad1a847180eebad3e47b2848cd8023adc 100644 (file)
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -470,7 +470,7 @@ struct SatGen
                        {
                                std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
                                std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
-                               extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0");
+                               extendSignalWidthUnary(undef_a, undef_y, cell);
 
                                if (cell->type == "$pos" || cell->type == "$bu0") {
                                        ez->assume(ez->vec_eq(undef_a, undef_y));