Add self._bridge to m.submodules (fixing #4)

diff --git a/gram/core/__init__.py b/gram/core/__init__.py
index 5a0755642eb8c703c27e0ebfae6ee7dc25445b4c..16b022ef530c125ef1a094810308510d3c1ffd51 100644 (file)
--- a/gram/core/__init__.py
+++ b/gram/core/__init__.py
@@ -52,6 +52,8 @@ class gramCore(Peripheral, Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+        m.submodules += self._bridge
+
         m.submodules += self.dfii
         m.d.comb += self.dfii.master.connect(self._phy.dfi)
 

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 6e1ec0449a1da2e5fc2f6848336e9f96277e159f..cf1a9c93ac3888defd72f610b7ea8c57783c41a1 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -155,6 +155,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+        m.submodules += self._bridge
+
         tck = 2/(2*2*self._sys_clk_freq)
         nphases = 2
         databits = len(self.pads.dq.oe)