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+Date: Mon, 01 Jun 2020 11:46:27 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
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+X-Bugzilla-Severity: enhancement
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+Message-ID: <bug-336-13-RA5hp6MHJi@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>
+References: <bug-336-13@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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