move FPDIV, FPMUL (etc) to ISAFPHelpers class

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index dad55a1261eb9d1cd90594e1b48c1138475fd088..d51305b96ad396cbad760e8d69d14ac6393206a2 100644 (file)
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -214,58 +214,6 @@ def SINGLE(FRS):
 # XXX NOTE: these are very quick hacked functions for utterly basic
 # FP support
 
-def fp64toselectable(frt):
-    """convert FP number to 64 bit SelectableInt
-    """
-    b = struct.pack(">d", frt)
-    val = int.from_bytes(b, byteorder='big', signed=False)
-    return SelectableInt(val, 64)
-
-
-def FPSIN32(FRB):
-    from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
-    #FRB = DOUBLE(SINGLE(FRB))
-    result = math.sin(float(FRB))
-    cvt = fp64toselectable(result)
-    cvt = DOUBLE2SINGLE(cvt)
-    log ("FPSIN32", FRB, float(FRB), "=", result, cvt)
-    return cvt
-
-
-def FPCOS32(FRB):
-    from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
-    #FRB = DOUBLE(SINGLE(FRB))
-    result = math.cos(float(FRB))
-    cvt = fp64toselectable(result)
-    cvt = DOUBLE2SINGLE(cvt)
-    log ("FPCOS32", FRB, float(FRB), "=", result, cvt)
-    return cvt
-
-
-def FPADD32(FRA, FRB):
-    from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
-    #return FPADD64(FRA, FRB)
-    #FRA = DOUBLE(SINGLE(FRA))
-    #FRB = DOUBLE(SINGLE(FRB))
-    result = float(FRA) + float(FRB)
-    cvt = fp64toselectable(result)
-    cvt = DOUBLE2SINGLE(cvt)
-    log ("FPADD32", FRA, FRB, float(FRA), "+", float(FRB), "=", result, cvt)
-    return cvt
-
-
-def FPSUB32(FRA, FRB):
-    from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
-    #return FPSUB64(FRA, FRB)
-    #FRA = DOUBLE(SINGLE(FRA))
-    #FRB = DOUBLE(SINGLE(FRB))
-    result = float(FRA) - float(FRB)
-    cvt = fp64toselectable(result)
-    cvt = DOUBLE2SINGLE(cvt)
-    log ("FPSUB32", FRA, FRB, float(FRA), "-", float(FRB), "=", result, cvt)
-    return cvt
-
-
 def signinv(res, sign):
     if sign == 1:
         return res
@@ -275,56 +223,98 @@ def signinv(res, sign):
         return -res
 
 
-def FPMUL32(FRA, FRB, sign=1):
-    #return FPMUL64(FRA, FRB)
-    FRA = DOUBLE(SINGLE(FRA))
-    FRB = DOUBLE(SINGLE(FRB))
-    result = signinv(float(FRA) * float(FRB), sign)
-    log ("FPMUL32", FRA, FRB, float(FRA), float(FRB), result, sign)
-    cvt = fp64toselectable(result)
-    cvt = DOUBLE2SINGLE(cvt)
-    log ("      cvt", cvt)
-    return cvt
-
-
-def FPMULADD32(FRA, FRC, FRB, mulsign, addsign):
-    from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
-    #return FPMUL64(FRA, FRB)
-    #FRA = DOUBLE(SINGLE(FRA))
-    #FRB = DOUBLE(SINGLE(FRB))
-    if addsign == 1:
-        if mulsign == 1:
-            result = float(FRA) * float(FRC) + float(FRB) # fmadds
-        elif mulsign == -1:
-            result = -(float(FRA) * float(FRC) - float(FRB))  # fnmsubs
-    elif addsign == -1:
-        if mulsign == 1:
-            result = float(FRA) * float(FRC) - float(FRB) # fmsubs
-        elif mulsign == -1:
-            result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
-    elif addsign == 0:
-        result = 0.0
-    log ("FPMULADD32 FRA FRC FRB", FRA, FRC, FRB)
-    log ("      FRA", float(FRA))
-    log ("      FRC", float(FRC))
-    log ("      FRB", float(FRB))
-    log ("      (FRA*FRC)+FRB=", mulsign, addsign, result)
-    cvt = fp64toselectable(result)
-    cvt = DOUBLE2SINGLE(cvt)
-    log ("      cvt", cvt)
-    return cvt
+def fp64toselectable(frt):
+    """convert FP number to 64 bit SelectableInt
+    """
+    b = struct.pack(">d", frt)
+    val = int.from_bytes(b, byteorder='big', signed=False)
+    return SelectableInt(val, 64)
 
 
-def FPDIV32(FRA, FRB, sign=1):
-    from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
-    #return FPDIV64(FRA, FRB)
-    #FRA = DOUBLE(SINGLE(FRA))
-    #FRB = DOUBLE(SINGLE(FRB))
-    result = signinv(float(FRA) / float(FRB), sign)
-    cvt = fp64toselectable(result)
-    cvt = DOUBLE2SINGLE(cvt)
-    log ("FPDIV32", FRA, FRB, result, cvt)
-    return cvt
+class ISAFPHelpers:
+
+    def FPSIN32(self, FRB):
+        #FRB = DOUBLE(SINGLE(FRB))
+        result = math.sin(float(FRB))
+        cvt = fp64toselectable(result)
+        cvt = self.DOUBLE2SINGLE(cvt)
+        log ("FPSIN32", FRB, float(FRB), "=", result, cvt)
+        return cvt
+
+    def FPCOS32(self, FRB):
+        #FRB = DOUBLE(SINGLE(FRB))
+        result = math.cos(float(FRB))
+        cvt = fp64toselectable(result)
+        cvt = self.DOUBLE2SINGLE(cvt)
+        log ("FPCOS32", FRB, float(FRB), "=", result, cvt)
+        return cvt
+
+    def FPADD32(self, FRA, FRB):
+        #return FPADD64(FRA, FRB)
+        #FRA = DOUBLE(SINGLE(FRA))
+        #FRB = DOUBLE(SINGLE(FRB))
+        result = float(FRA) + float(FRB)
+        cvt = fp64toselectable(result)
+        cvt = self.DOUBLE2SINGLE(cvt)
+        log ("FPADD32", FRA, FRB, float(FRA), "+", float(FRB), "=", result, cvt)
+        return cvt
+
+    def FPSUB32(self, FRA, FRB):
+        #return FPSUB64(FRA, FRB)
+        #FRA = DOUBLE(SINGLE(FRA))
+        #FRB = DOUBLE(SINGLE(FRB))
+        result = float(FRA) - float(FRB)
+        cvt = fp64toselectable(result)
+        cvt = self.DOUBLE2SINGLE(cvt)
+        log ("FPSUB32", FRA, FRB, float(FRA), "-", float(FRB), "=", result, cvt)
+        return cvt
+
+    def FPMUL32(self, FRA, FRB, sign=1):
+        #return FPMUL64(FRA, FRB)
+        FRA = self.DOUBLE(SINGLE(FRA))
+        FRB = self.DOUBLE(SINGLE(FRB))
+        result = signinv(float(FRA) * float(FRB), sign)
+        log ("FPMUL32", FRA, FRB, float(FRA), float(FRB), result, sign)
+        cvt = fp64toselectable(result)
+        cvt = self.DOUBLE2SINGLE(cvt)
+        log ("      cvt", cvt)
+        return cvt
+
+    def FPMULADD32(self, FRA, FRC, FRB, mulsign, addsign):
+        #return FPMUL64(FRA, FRB)
+        #FRA = DOUBLE(SINGLE(FRA))
+        #FRB = DOUBLE(SINGLE(FRB))
+        if addsign == 1:
+            if mulsign == 1:
+                result = float(FRA) * float(FRC) + float(FRB) # fmadds
+            elif mulsign == -1:
+                result = -(float(FRA) * float(FRC) - float(FRB))  # fnmsubs
+        elif addsign == -1:
+            if mulsign == 1:
+                result = float(FRA) * float(FRC) - float(FRB) # fmsubs
+            elif mulsign == -1:
+                result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
+        elif addsign == 0:
+            result = 0.0
+        log ("FPMULADD32 FRA FRC FRB", FRA, FRC, FRB)
+        log ("      FRA", float(FRA))
+        log ("      FRC", float(FRC))
+        log ("      FRB", float(FRB))
+        log ("      (FRA*FRC)+FRB=", mulsign, addsign, result)
+        cvt = fp64toselectable(result)
+        cvt = self.DOUBLE2SINGLE(cvt)
+        log ("      cvt", cvt)
+        return cvt
+
+    def FPDIV32(self, FRA, FRB, sign=1):
+        #return FPDIV64(FRA, FRB)
+        #FRA = DOUBLE(SINGLE(FRA))
+        #FRB = DOUBLE(SINGLE(FRB))
+        result = signinv(float(FRA) / float(FRB), sign)
+        cvt = fp64toselectable(result)
+        cvt = self.DOUBLE2SINGLE(cvt)
+        log ("FPDIV32", FRA, FRB, result, cvt)
+        return cvt
 
 
 def FPADD64(FRA, FRB):

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 100b686c23c95e03cf39dc197a501928fad3c103..e330fb28e03374732b96c4a8635834d19c90991c 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -29,7 +29,7 @@ from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
 from openpower.decoder.power_enums import SVPtype
 
 from openpower.decoder.helpers import (exts, gtu, ltu, undefined,
-                                       ISACallerHelper)
+                                       ISACallerHelper, ISAFPHelpers)
 from openpower.consts import PIb, MSRb  # big-endian (PowerISA versions)
 from openpower.consts import (SVP64MODE,
                               SVP64CROffs,
@@ -560,7 +560,7 @@ def get_pdecode_idx_out2(dec2, name):
     return None, False
 
 
-class ISACaller(ISACallerHelper):
+class ISACaller(ISACallerHelper, ISAFPHelpers):
     # decoder2 - an instance of power_decoder2
     # regfile - a list of initial values for the registers
     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR

diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py
index 70e87374420301415707fa6edfa1a18293319635..b2215d38aa8e9abf81f9dd778c317a5be3f37140 100644 (file)
--- a/src/openpower/decoder/pseudo/parser.py
+++ b/src/openpower/decoder/pseudo/parser.py
@@ -27,6 +27,7 @@ regs = ['RA', 'RS', 'RB', 'RC', 'RT']
 fregs = ['FRA', 'FRS', 'FRB', 'FRC', 'FRT', 'FRS']
 SPECIAL_HELPERS = {'concat', 'MEM', 'GPR', 'FPR', 'SPR'}
 
+
 def Assign(autoassign, assignname, left, right, iea_mode):
     names = []
     print("Assign", autoassign, assignname, left, right)