uart: Enable buffering the FIFO.

On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index 3e88e7ae95da566d19b21a986aea6afdb2f60587..a5305e6a83438fd9a427307efe711faa57935747 100644 (file)
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -157,7 +157,7 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
         fifo = stream.AsyncFIFO([("data", 8)], depth)
         return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
     else:
-        return stream.SyncFIFO([("data", 8)], depth)
+        return stream.SyncFIFO([("data", 8)], depth, buffered=True)
 
 
 class UART(Module, AutoCSR):