integration/soc_core: expose more SoC parameters

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 1be23874a4ad4a8960fd02c4be08c670e860913e..9e307518047f42720c75bc5056c13aa8aa284d31 100644 (file)
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -278,7 +278,7 @@ class XilinxVivadoToolchain:
             self.false_paths.add((from_, to))
 
 def vivado_build_args(parser):
-    parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (vivado or yosys)")
+    parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (vivado or yosys, default=vivado)")
 
 
 def vivado_build_argdict(args):

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index ef9854a7ed34ff3e2d0bee31cf1798214b692113..63db68e7abbf4ba84145a49ffbbda21c790faf55 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -513,17 +513,47 @@ class SoCCore(Module):
 # SoCCore arguments --------------------------------------------------------------------------------
 
 def soc_core_args(parser):
+    # CPU parameters
     parser.add_argument("--cpu-type", default=None,
                         help="select CPU: {}".format(", ".join(iter(cpu.CPUS.keys()))))
     parser.add_argument("--cpu-variant", default=None,
-                        help="select CPU variant")
+                        help="select CPU variant, (default=standard)")
+    parser.add_argument("--cpu-reset-address", default=None, type=int,
+                        help="CPU reset address (default=0x00000000 or ROM)")
+    # ROM parameters
     parser.add_argument("--integrated-rom-size", default=None, type=int,
                         help="size/enable the integrated (BIOS) ROM")
+    # SRAM parameters
+    parser.add_argument("--integrated_sram_size", default=None,
+                        help="size/enable the integrated SRAM")
+    # MAIN_RAM parameters
     parser.add_argument("--integrated-main-ram-size", default=None, type=int,
                         help="size/enable the integrated main RAM")
+    # CSR parameters
+    parser.add_argument("--csr-data-width", default=None, type=int,
+                        help="CSR bus data-width (8 or 32, default=8)")
+    parser.add_argument("--csr-address-width", default=14, type=int,
+                        help="CSR bus address-width")
+    # Identifier parameters
+    parser.add_argument("--ident", default=None, type=str,
+                        help="SoC identifier (default=\"\"")
+    parser.add_argument("--ident-version", default=None, type=bool,
+                        help="add date/time to SoC identifier (default=False)")
+    # UART parameters
+    parser.add_argument("--with-uart", default=None, type=bool,
+                        help="with UART (default=True)")
+    parser.add_argument("--uart-name", default="\"serial\"", type=str,
+                        help="UART type/name (default=serial)")
+    parser.add_argument("--uart-baudrate", default=None, type=int,
+                        help="UART baudrate (default=115200)")
     parser.add_argument("--uart-stub", default=False, type=bool,
-                        help="enable uart stub")
-
+                        help="enable UART stub (default=False)")
+    # Timer parameters
+    parser.add_argument("--with-timer", default=None, type=bool,
+                        help="with Timer (default=True)")
+    # Controller parameters
+    parser.add_argument("--with-ctrl", default=None, type=bool,
+                        help="with Controller (default=True)")
 
 def soc_core_argdict(args):
     r = dict()