elif buildEnv['TARGET_ISA'] == 'x86':
return env.get('LINUX_IMAGE', disk('x86root.img'))
elif buildEnv['TARGET_ISA'] == 'arm':
- return env.get('LINUX_IMAGE', disk('ael-arm.ext2'))
+ return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
else:
print "Don't know what default disk image to use for ISA %s" % \
buildEnv['TARGET_ISA']
'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],
'MutexTest': [SysConfig('mutex-test.rcS', '128MB')],
- 'ArmLinux': [SysConfig('null.rcS', '128MB', 'ael-arm.ext2')],
- 'ArmLinuxFrameBuf': [SysConfig('null.rcS', '128MB', 'ael-full.ext2')],
- 'ArmLinuxCflash': [SysConfig('null.rcS', '256MB', 'linux-arm.img')],
'ArmAndroid': [SysConfig('null.rcS', '256MB', 'android-mbr.img')],
}
from m5.objects import *
from Benchmarks import *
+from m5.util import convert
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
print "Unknown Machine Type"
sys.exit(1)
- use_cf = False
- if mdesc.disk()[-4:] == ".img":
- use_cf = True
- self.cf0 = CowIdeDisk(driveID='master')
- self.cf0.childImage(mdesc.disk())
- # default to an IDE controller rather than a CF one
- # assuming we've got one
- try:
- self.realview.ide.disks = [self.cf0]
- except:
- self.realview.cf_ctrl.disks = [self.cf0]
+ self.cf0 = CowIdeDisk(driveID='master')
+ self.cf0.childImage(mdesc.disk())
+ # default to an IDE controller rather than a CF one
+ # assuming we've got one
+ try:
+ self.realview.ide.disks = [self.cf0]
+ except:
+ self.realview.cf_ctrl.disks = [self.cf0]
+
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
- self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
zero = True)
else:
- self.kernel = binary('vmlinux.arm')
+ self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
self.machine_type = machine_type
+ if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
+ print "The currently implemented ARM platforms only easily support 256MB of DRAM"
+ print "It might be possible to get some more by using 256MB@0x30000000, but this"
+ print "is untested and may require some heroics"
+
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
- 'rw loglevel=8 '
- if use_cf:
- self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
- zero = True)
- boot_flags += "mem=256MB root=/dev/sda1 "
- self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
- size = '64MB'), zero = True)
- self.nvmem.port = self.membus.port
- self.boot_loader = binary('boot.arm')
- self.boot_loader_mem = self.nvmem
- self.gic_cpu_addr = self.realview.gic.cpu_addr
- self.flags_addr = self.realview.realview_io.pio_addr + 0x30
- else:
- self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')),
- zero = True)
- self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'),
- size = '128MB'),
- file = disk(mdesc.disk()))
- self.diskmem.port = self.membus.port
- boot_flags += "mem=128MB slram=slram0,0x8000000,+0x8000000 " + \
- "mtdparts=slram0:- root=/dev/mtdblock0 "
+ 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
+
+ self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
+ self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
+ size = '64MB'), zero = True)
+ self.nvmem.port = self.membus.port
+ self.boot_loader = binary('boot.arm')
+ self.boot_loader_mem = self.nvmem
+ self.gic_cpu_addr = self.realview.gic.cpu_addr
+ self.flags_addr = self.realview.realview_io.pio_addr + 0x30
if mdesc.disk().count('android'):
boot_flags += "init=/init "
't1000-simple-timing']
if env['TARGET_ISA'] == 'arm':
configs += ['realview-simple-atomic',
+ 'realview-simple-atomic-dual',
'realview-simple-timing',
- 'realview-o3']
+ 'realview-simple-timing-dual',
+ 'realview-o3',
+ 'realview-o3-dual']
if env['TARGET_ISA'] == 'x86':
configs += ['pc-simple-atomic',
'pc-simple-timing',
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='256MB')
+ forward_snoops = False
+
+#cpu
+cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+system.l2c.num_cpus = 2
+
+#connect up the cpu and l1s
+for c in cpus:
+ c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+ # connect cpu level-1 caches to shared level-2 cache
+ c.connectAllPorts(system.toL2Bus, system.membus)
+ c.clock = '2GHz'
+
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
- addr_range=AddrRange(0, size='128MB')
+ addr_range=AddrRange(0, size='256MB')
forward_snoops = False
#cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
-system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='256MB')
+ forward_snoops = False
+
+#cpu
+cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+system.l2c.num_cpus = 2
+
+#connect up the cpu and l1s
+for c in cpus:
+ c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+ # connect cpu level-1 caches to shared level-2 cache
+ c.connectAllPorts(system.toL2Bus, system.membus)
+ c.clock = '2GHz'
+
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
- addr_range=AddrRange(0, size='128MB')
+ addr_range=AddrRange(0, size='256MB')
forward_snoops = False
#cpu
#the system
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
-system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Benchmarks import *
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='256MB')
+ forward_snoops = False
+
+#cpu
+cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+system.l2c.num_cpus = 2
+
+#connect up the cpu and l1s
+for c in cpus:
+ c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+ # connect cpu level-1 caches to shared level-2 cache
+ c.connectAllPorts(system.toL2Bus, system.membus)
+ c.clock = '2GHz'
+
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
- addr_range=AddrRange(0, size='128MB')
+ addr_range=AddrRange(0, size='256MB')
forward_snoops = False
#cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
-system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
--- /dev/null
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
+boot_cpu_frequency=500
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=timing
+memories=system.nvmem system.physmem
+midr_regval=890224640
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:268435455
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=DerivO3CPU
+children=dcache dtb fuPool icache interrupts itb tracer
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu0.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+interrupts=system.cpu0.interrupts
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu0.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu0.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[4]
+
+[system.cpu0.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
+
+[system.cpu0.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu0.fuPool.FUList0.opList
+
+[system.cpu0.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
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+port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:268435455
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+is_top_level=false
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[25]
+mem_side=system.membus.port[7]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=2
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[8]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.realview
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=true
+port=system.membus.port[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268451840
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=1000
+platform=system.realview
+system=system
+config=system.iobus.port[26]
+dma=system.iobus.port[27]
+pio=system.iobus.port[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=41667
+gic=system.realview.gic
+int_num=55
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pio_addr=268566528
+pio_latency=10000
+platform=system.realview
+system=system
+vnc=system.vncserver
+dma=system.iobus.port[28]
+pio=system.iobus.port[5]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268632064
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+fake_mem=true
+pio_addr=1073741824
+pio_latency=1000
+pio_size=536870912
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[24]
+
+[system.realview.gic]
+type=Gic
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.port[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268513280
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268517376
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268521472
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+fake_mem=false
+pio_addr=520101888
+pio_latency=1000
+pio_size=4095
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.port[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268455936
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[22]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+idreg=0
+pio_addr=268435456
+pio_latency=1000
+platform=system.realview
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.port[2]
+
+[system.realview.rtc_fake]
+type=AmbaFake
+amba_id=266289
+ignore_access=false
+pio_addr=268529664
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268492800
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=269357056
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=true
+pio_addr=268439552
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268488704
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[3]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[4]
+
+[system.realview.uart]
+type=Pl011
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=1000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.port[1]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268476416
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268480512
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268484608
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268500992
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+number=0
+port=5900
+
--- /dev/null
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr dccimvac' unimplemented
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
+warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 2582677547500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.582678 # Number of seconds simulated
+sim_ticks 2582677547500 # Number of ticks simulated
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 75295 # Simulator instruction rate (inst/s)
+host_tick_rate 2435818565 # Simulator tick rate (ticks/s)
+host_mem_usage 423776 # Number of bytes of host memory used
+host_seconds 1060.29 # Real time elapsed on the host
+sim_insts 79834358 # Number of instructions simulated
+system.l2c.replacements 130785 # number of replacements
+system.l2c.tagsinuse 27318.484309 # Cycle average of tags in use
+system.l2c.total_refs 1826531 # Total number of references to valid blocks.
+system.l2c.sampled_refs 161304 # Sample count of references to valid blocks.
+system.l2c.avg_refs 11.323532 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 5406.863178 # Average occupied blocks per context
+system.l2c.occ_blocks::1 6677.424533 # Average occupied blocks per context
+system.l2c.occ_blocks::2 15234.196598 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.082502 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.101889 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.232455 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 803697 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 562068 # number of ReadReq hits
+system.l2c.ReadReq_hits::2 188134 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1553899 # number of ReadReq hits
+system.l2c.Writeback_hits::0 603483 # number of Writeback hits
+system.l2c.Writeback_hits::total 603483 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 1202 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 810 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 2012 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0 219 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1 351 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 570 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0 63626 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 37284 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 100910 # number of ReadExReq hits
+system.l2c.demand_hits::0 867323 # number of demand (read+write) hits
+system.l2c.demand_hits::1 599352 # number of demand (read+write) hits
+system.l2c.demand_hits::2 188134 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1654809 # number of demand (read+write) hits
+system.l2c.overall_hits::0 867323 # number of overall hits
+system.l2c.overall_hits::1 599352 # number of overall hits
+system.l2c.overall_hits::2 188134 # number of overall hits
+system.l2c.overall_hits::total 1654809 # number of overall hits
+system.l2c.ReadReq_misses::0 22876 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 16980 # number of ReadReq misses
+system.l2c.ReadReq_misses::2 159 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 40015 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 6837 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 3470 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 10307 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0 768 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 499 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1267 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0 99026 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 49105 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 148131 # number of ReadExReq misses
+system.l2c.demand_misses::0 121902 # number of demand (read+write) misses
+system.l2c.demand_misses::1 66085 # number of demand (read+write) misses
+system.l2c.demand_misses::2 159 # number of demand (read+write) misses
+system.l2c.demand_misses::total 188146 # number of demand (read+write) misses
+system.l2c.overall_misses::0 121902 # number of overall misses
+system.l2c.overall_misses::1 66085 # number of overall misses
+system.l2c.overall_misses::2 159 # number of overall misses
+system.l2c.overall_misses::total 188146 # number of overall misses
+system.l2c.ReadReq_miss_latency 2090784500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency 57155000 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency 7364000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency 7771362499 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency 9862146999 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 9862146999 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 826573 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 579048 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2 188293 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1593914 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 603483 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 603483 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 8039 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 4280 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 12319 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0 987 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1 850 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1837 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 162652 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1 86389 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 249041 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 989225 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 665437 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 188293 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1842955 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 989225 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 665437 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 188293 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1842955 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.027676 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.029324 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2 0.000844 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.057844 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.850479 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.810748 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0 0.778116 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1 0.587059 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.608821 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.568417 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.123230 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.099311 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 0.000844 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.223385 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.123230 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.099311 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 0.000844 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.223385 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 91396.419829 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 123132.184923 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2 13149588.050314 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 13364116.655067 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 8359.660670 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 16471.181556 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::0 9588.541667 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1 14757.515030 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 78478.000717 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 158260.105875 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0 80902.257543 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 149234.274026 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 62026081.754717 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 62256218.286286 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 80902.257543 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 149234.274026 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 62026081.754717 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 62256218.286286 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 111655 # number of writebacks
+system.l2c.ReadReq_mshr_hits 99 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits 99 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 99 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses 39916 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 10307 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses 1267 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 148131 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 188047 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 188047 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency 1599541500 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 412620000 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency 50764500 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5935595999 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 7535137499 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 7535137499 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 131969781000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 32516901535 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 164486682535 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.048291 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.068934 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2 0.211989 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.329214 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 1.282125 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 2.408178 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.283688 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.490588 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 0.910724 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1 1.714697 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0 0.190095 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0.282592 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 0.998694 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 1.471381 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.190095 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0.282592 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 0.998694 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 1.471381 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40072.690149 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40032.987290 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40066.692976 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40069.911085 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 41192849 # DTB read hits
+system.cpu0.dtb.read_misses 63693 # DTB read misses
+system.cpu0.dtb.write_hits 7450240 # DTB write hits
+system.cpu0.dtb.write_misses 14279 # DTB write misses
+system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 2696 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 5912 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 640 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 1671 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 41256542 # DTB read accesses
+system.cpu0.dtb.write_accesses 7464519 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 48643089 # DTB hits
+system.cpu0.dtb.misses 77972 # DTB misses
+system.cpu0.dtb.accesses 48721061 # DTB accesses
+system.cpu0.itb.inst_hits 7154156 # ITB inst hits
+system.cpu0.itb.inst_misses 18344 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 1605 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 6284 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 7172500 # ITB inst accesses
+system.cpu0.itb.hits 7154156 # DTB hits
+system.cpu0.itb.misses 18344 # DTB misses
+system.cpu0.itb.accesses 7172500 # DTB accesses
+system.cpu0.numCycles 357540967 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.BPredUnit.lookups 9593725 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 7120843 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 688397 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 8086863 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 5605356 # Number of BTB hits
+system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.BPredUnit.usedRAS 917445 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 151480 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 18599757 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 50204356 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 9593725 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 6522801 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 12725278 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3026243 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 114823 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 80197472 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 119675 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 131982 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 222 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7147681 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 329179 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 9806 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 114004183 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.572281 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.836691 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 101298717 88.86% 88.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 1249230 1.10% 89.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1702654 1.49% 91.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1440887 1.26% 92.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1218688 1.07% 93.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 996216 0.87% 94.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 913152 0.80% 95.45% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 546684 0.48% 95.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4637955 4.07% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total 114004183 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.026833 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.140416 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 19798941 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 79925582 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 11493306 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 769981 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2016373 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1516743 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 98250 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 62465027 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 321354 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 2016373 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 20942863 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 33418227 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 41890543 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 11135381 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 4600796 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 59851687 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1820 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 622371 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 3206696 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 196 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 60092077 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 271645522 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 271595503 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 50019 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 44620651 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 15471425 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 873594 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 797183 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 8821523 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 12757061 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 8422181 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1717649 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1992572 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 55833489 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1355727 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 82528607 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 169777 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 11480759 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 26808481 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 257868 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 114004183 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.723909 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.428339 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 83031906 72.83% 72.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10859028 9.53% 82.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4622462 4.05% 86.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3473838 3.05% 89.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 9590269 8.41% 97.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1336341 1.17% 99.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 758222 0.67% 99.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 245908 0.22% 99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 86209 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 114004183 # Number of insts issued each cycle
+system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 40984 0.54% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 430 0.01% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 7316558 95.62% 96.16% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 293687 3.84% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu0.iq.FU_type_0::No_OpClass 88545 0.11% 0.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 32461139 39.33% 39.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 66584 0.08% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 1699 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 39.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 41999048 50.89% 90.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 7911577 9.59% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total 82528607 # Type of FU issued
+system.cpu0.iq.rate 0.230823 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 7651659 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.092715 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 286948190 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 68723133 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 50664328 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 11541 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 7288 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5232 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 90085763 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 5958 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 417346 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.squashedLoads 2922980 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 6316 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 61885 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1142353 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread0.rescheduledLoads 30234184 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 13064 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu0.iew.iewSquashCycles 2016373 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 25967321 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 376582 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 57371840 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 294662 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 12757061 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 8422181 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 894783 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 65983 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 6042 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 61885 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 548006 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 156688 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 704694 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 81662256 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 41659868 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 866351 # Number of squashed instructions skipped in execute
+system.cpu0.iew.exec_swp 0 # number of swp insts executed
+system.cpu0.iew.exec_nop 182624 # number of nop insts executed
+system.cpu0.iew.exec_refs 49452351 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 7085446 # Number of branches executed
+system.cpu0.iew.exec_stores 7792483 # Number of stores executed
+system.cpu0.iew.exec_rate 0.228400 # Inst execution rate
+system.cpu0.iew.wb_sent 81169545 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 50669560 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 26746507 # num instructions producing a value
+system.cpu0.iew.wb_consumers 50218305 # num instructions consuming a value
+system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_rate 0.141717 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.532605 # average fanout of values written-back
+system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.commit.commitCommittedInsts 45235360 # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts 11991795 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1097859 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 616755 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 112037138 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.403753 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.265449 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 93611832 83.55% 83.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 10012247 8.94% 92.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2707975 2.42% 94.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1499111 1.34% 96.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1132088 1.01% 97.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 700448 0.63% 97.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 719513 0.64% 98.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 269232 0.24% 98.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1384692 1.24% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total 112037138 # Number of insts commited each cycle
+system.cpu0.commit.count 45235360 # Number of instructions committed
+system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu0.commit.refs 17113909 # Number of memory references committed
+system.cpu0.commit.loads 9834081 # Number of loads committed
+system.cpu0.commit.membars 304797 # Number of memory barriers committed
+system.cpu0.commit.branches 6085015 # Number of branches committed
+system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 40053285 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 683094 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1384692 # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu0.rob.rob_reads 166715497 # The number of ROB reads
+system.cpu0.rob.rob_writes 116483375 # The number of ROB writes
+system.cpu0.timesIdled 1500698 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 243536784 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 45109533 # Number of Instructions Simulated
+system.cpu0.committedInsts_total 45109533 # Number of Instructions Simulated
+system.cpu0.cpi 7.926062 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 7.926062 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.126166 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.126166 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 365152407 # number of integer regfile reads
+system.cpu0.int_regfile_writes 50032906 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 4200 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 1342 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 71323581 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 671757 # number of misc regfile writes
+system.cpu0.icache.replacements 594199 # number of replacements
+system.cpu0.icache.tagsinuse 511.628418 # Cycle average of tags in use
+system.cpu0.icache.total_refs 6500767 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 594711 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 10.930968 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 6436890000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0 511.628418 # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0 0.999274 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::0 6500767 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 6500767 # number of ReadReq hits
+system.cpu0.icache.demand_hits::0 6500767 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 6500767 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::0 6500767 # number of overall hits
+system.cpu0.icache.overall_hits::1 0 # number of overall hits
+system.cpu0.icache.overall_hits::total 6500767 # number of overall hits
+system.cpu0.icache.ReadReq_misses::0 646785 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 646785 # number of ReadReq misses
+system.cpu0.icache.demand_misses::0 646785 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 646785 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::0 646785 # number of overall misses
+system.cpu0.icache.overall_misses::1 0 # number of overall misses
+system.cpu0.icache.overall_misses::total 646785 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency 9658555994 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency 9658555994 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency 9658555994 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::0 7147552 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 7147552 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::0 7147552 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 7147552 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::0 7147552 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 7147552 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::0 0.090490 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::0 0.090490 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::0 0.090490 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::0 14933.178713 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::0 14933.178713 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::0 14933.178713 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 1667497 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 224 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 7444.183036 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.writebacks 31555 # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits 52053 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits 52053 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits 52053 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses 594732 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses 594732 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses 594732 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency 7219185997 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency 7219185997 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency 7219185997 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083208 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::0 0.083208 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::0 0.083208 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.553158 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.replacements 392671 # number of replacements
+system.cpu0.dcache.tagsinuse 483.584669 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 13959325 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 393183 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 35.503379 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0 486.484981 # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1 -2.900311 # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0 0.950166 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1 -0.005665 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::0 8695002 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 8695002 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::0 4786521 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 4786521 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0 223142 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 223142 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::0 209904 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 209904 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::0 13481523 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 13481523 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::0 13481523 # number of overall hits
+system.cpu0.dcache.overall_hits::1 0 # number of overall hits
+system.cpu0.dcache.overall_hits::total 13481523 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::0 481329 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 481329 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::0 1933412 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1933412 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::0 10228 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 10228 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::0 7385 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7385 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::0 2414741 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 2414741 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::0 2414741 # number of overall misses
+system.cpu0.dcache.overall_misses::1 0 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2414741 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency 6831199500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency 71775006335 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency 125537000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency 81774000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency 78606205835 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency 78606205835 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::0 9176331 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 9176331 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::0 6719933 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 6719933 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::0 233370 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 233370 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::0 217289 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 217289 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::0 15896264 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 15896264 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::0 15896264 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 15896264 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::0 0.052453 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::0 0.287713 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043827 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.033987 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::0 0.151906 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::0 0.151906 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 14192.370499 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 37123.492735 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12273.856081 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11072.985782 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::0 32552.644708 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::0 32552.644708 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 7515481 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 2368000 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 844 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8904.598341 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 18076.335878 # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks 345751 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits 230083 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits 1750706 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits 435 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits 1980789 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits 1980789 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses 251246 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses 182706 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses 9793 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses 7384 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses 433952 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses 433952 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency 3167466500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency 6457872480 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 89563500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 59583000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency 9625338980 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency 9625338980 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 139101280000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1100636486 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency 140201916486 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.027380 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.027189 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041963 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.033982 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::0 0.027299 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::0 0.027299 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12607.032550 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35345.705560 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9145.665271 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8069.203684 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 9398153 # DTB read hits
+system.cpu1.dtb.read_misses 34944 # DTB read misses
+system.cpu1.dtb.write_hits 4980209 # DTB write hits
+system.cpu1.dtb.write_misses 12567 # DTB write misses
+system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 7467 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 777 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 9433097 # DTB read accesses
+system.cpu1.dtb.write_accesses 4992776 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 14378362 # DTB hits
+system.cpu1.dtb.misses 47511 # DTB misses
+system.cpu1.dtb.accesses 14425873 # DTB accesses
+system.cpu1.itb.inst_hits 7673879 # ITB inst hits
+system.cpu1.itb.inst_misses 3663 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 1371 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 2297 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 7677542 # ITB inst accesses
+system.cpu1.itb.hits 7673879 # DTB hits
+system.cpu1.itb.misses 3663 # DTB misses
+system.cpu1.itb.accesses 7677542 # DTB accesses
+system.cpu1.numCycles 64448888 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.BPredUnit.lookups 7492397 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 6087986 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 429995 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 6556371 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 5183364 # Number of BTB hits
+system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.BPredUnit.usedRAS 581252 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 90679 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 16050492 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 59173184 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7492397 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5764616 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 12912375 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 4437648 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 50354 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 14454862 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 2217 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 33931 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 110303 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7671208 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 720838 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2326 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 46632146 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.521202 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.768696 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 33727851 72.33% 72.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 606934 1.30% 73.63% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 1038343 2.23% 75.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 2380602 5.11% 80.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1071399 2.30% 83.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 528430 1.13% 84.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1841086 3.95% 88.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 362782 0.78% 89.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5074719 10.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total 46632146 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.116253 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.918141 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 17056644 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 14680691 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 11594841 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 352795 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2947175 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 935072 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 71695 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 65351582 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 230259 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2947175 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 18144332 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 3419554 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 9765064 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 10859095 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 1496926 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 59649280 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 2711 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 296113 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 846856 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 41886 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 64117293 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 277536206 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 277482920 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 53286 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 35880340 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 28236953 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 382644 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 338532 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 3807140 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 10355028 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6398549 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 758675 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 956516 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 52234406 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 583658 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 46076403 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 106678 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 17743407 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 51695034 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 121990 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 46632146 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.988082 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.605820 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 29554282 63.38% 63.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 5171149 11.09% 74.47% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3458614 7.42% 81.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3350013 7.18% 89.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 2774412 5.95% 95.02% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1396410 2.99% 98.01% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 685832 1.47% 99.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 188175 0.40% 99.89% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 53259 0.11% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 46632146 # Number of insts issued each cycle
+system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 13884 1.72% 1.72% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 1004 0.12% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 591453 73.41% 75.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 199352 24.74% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu1.iq.FU_type_0::No_OpClass 18555 0.04% 0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 30356671 65.88% 65.92% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 45470 0.10% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 778 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 10369047 22.50% 88.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 5285878 11.47% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total 46076403 # Type of FU issued
+system.cpu1.iq.rate 0.714929 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 805693 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.017486 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 139732039 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 70588254 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 40690264 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 12584 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 7193 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 5833 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 46856971 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6570 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 234193 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.squashedLoads 3842003 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 5600 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 34715 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1441399 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread0.rescheduledLoads 1340152 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 1120623 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu1.iew.iewSquashCycles 2947175 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 2308626 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 70118 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 52866942 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 210917 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 10355028 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6398549 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 369018 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 28955 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3115 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 34715 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 320337 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 109623 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 429960 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 43402987 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 9638435 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2673416 # Number of squashed instructions skipped in execute
+system.cpu1.iew.exec_swp 0 # number of swp insts executed
+system.cpu1.iew.exec_nop 48878 # number of nop insts executed
+system.cpu1.iew.exec_refs 14847152 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5186837 # Number of branches executed
+system.cpu1.iew.exec_stores 5208717 # Number of stores executed
+system.cpu1.iew.exec_rate 0.673448 # Inst execution rate
+system.cpu1.iew.wb_sent 42199254 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 40696097 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 22507628 # num instructions producing a value
+system.cpu1.iew.wb_consumers 40593312 # num instructions consuming a value
+system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_rate 0.631448 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.554466 # average fanout of values written-back
+system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.commit.commitCommittedInsts 34749379 # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts 18015602 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 461668 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 380980 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 43720356 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.794810 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.823117 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 31867002 72.89% 72.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 5587415 12.78% 85.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1616564 3.70% 89.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 871952 1.99% 91.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 744460 1.70% 93.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 803606 1.84% 94.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 559765 1.28% 96.18% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 398216 0.91% 97.09% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1271376 2.91% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total 43720356 # Number of insts commited each cycle
+system.cpu1.commit.count 34749379 # Number of instructions committed
+system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu1.commit.refs 11470175 # Number of memory references committed
+system.cpu1.commit.loads 6513025 # Number of loads committed
+system.cpu1.commit.membars 132167 # Number of memory barriers committed
+system.cpu1.commit.branches 4257777 # Number of branches committed
+system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 31123411 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 369866 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1271376 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu1.rob.rob_reads 94544262 # The number of ROB reads
+system.cpu1.rob.rob_writes 108591524 # The number of ROB writes
+system.cpu1.timesIdled 403013 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 17816742 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.committedInsts 34724825 # Number of Instructions Simulated
+system.cpu1.committedInsts_total 34724825 # Number of Instructions Simulated
+system.cpu1.cpi 1.855989 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.855989 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.538796 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.538796 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 204029035 # number of integer regfile reads
+system.cpu1.int_regfile_writes 43806802 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 4161 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 72521776 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 283678 # number of misc regfile writes
+system.cpu1.icache.replacements 430439 # number of replacements
+system.cpu1.icache.tagsinuse 498.734431 # Cycle average of tags in use
+system.cpu1.icache.total_refs 7202456 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 430951 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 16.712935 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 74509623000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0 498.734431 # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0 0.974091 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::0 7202456 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 7202456 # number of ReadReq hits
+system.cpu1.icache.demand_hits::0 7202456 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 7202456 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::0 7202456 # number of overall hits
+system.cpu1.icache.overall_hits::1 0 # number of overall hits
+system.cpu1.icache.overall_hits::total 7202456 # number of overall hits
+system.cpu1.icache.ReadReq_misses::0 468704 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 468704 # number of ReadReq misses
+system.cpu1.icache.demand_misses::0 468704 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 468704 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::0 468704 # number of overall misses
+system.cpu1.icache.overall_misses::1 0 # number of overall misses
+system.cpu1.icache.overall_misses::total 468704 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency 6861113492 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency 6861113492 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency 6861113492 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::0 7671160 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 7671160 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::0 7671160 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 7671160 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::0 7671160 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 7671160 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::0 0.061099 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::0 0.061099 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::0 0.061099 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14638.478639 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::0 14638.478639 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::0 14638.478639 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 1040994 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 141 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 7382.936170 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.writebacks 18963 # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits 37728 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits 37728 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits 37728 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses 430976 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses 430976 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses 430976 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency 5122297994 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency 5122297994 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency 5122297994 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.056181 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::0 0.056181 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::0 0.056181 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11885.343950 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.replacements 254482 # number of replacements
+system.cpu1.dcache.tagsinuse 445.587784 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 9324863 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 254845 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 36.590331 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0 446.560833 # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1 -0.973049 # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0 0.872189 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::1 -0.001900 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::0 6489866 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 6489866 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::0 2669080 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 2669080 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::0 65573 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 65573 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::0 63091 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 63091 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::0 9158946 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 9158946 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::0 9158946 # number of overall hits
+system.cpu1.dcache.overall_hits::1 0 # number of overall hits
+system.cpu1.dcache.overall_hits::total 9158946 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::0 299965 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 299965 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::0 1235939 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1235939 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::0 11914 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 11914 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::0 10340 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10340 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::0 1535904 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 1535904 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::0 1535904 # number of overall misses
+system.cpu1.dcache.overall_misses::1 0 # number of overall misses
+system.cpu1.dcache.overall_misses::total 1535904 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency 4645144000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency 45196829928 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency 137229500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency 85681500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency 49841973928 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency 49841973928 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::0 6789831 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 6789831 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::0 3905019 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 3905019 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::0 77487 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 77487 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::0 73431 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 73431 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::0 10694850 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 10694850 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::0 10694850 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 10694850 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::0 0.044179 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::0 0.316500 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.153755 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::0 0.140812 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::0 0.143612 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::0 0.143612 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 15485.619989 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 36568.819277 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11518.339768 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8286.411992 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::0 32451.229978 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::0 32451.229978 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 10791088 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 5629500 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 2675 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4034.051589 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 33912.650602 # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks 207215 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits 126705 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits 1124640 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits 1020 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits 1251345 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits 1251345 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses 173260 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses 111299 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses 10894 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses 10338 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses 284559 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses 284559 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency 2232969500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency 3340467088 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 89924500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54610500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency 5573436588 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency 5573436588 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8313873500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41408758936 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency 49722632436 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025518 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.028502 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140591 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.140785 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::0 0.026607 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0 0.026607 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12887.968948 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 30013.451046 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8254.497889 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5282.501451 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.avg_refs no_value # Average number of references to valid blocks.
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.demand_hits::0 0 # number of demand (read+write) hits
+system.iocache.demand_hits::1 0 # number of demand (read+write) hits
+system.iocache.demand_hits::total 0 # number of demand (read+write) hits
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
+system.iocache.demand_misses::0 0 # number of demand (read+write) misses
+system.iocache.demand_misses::1 0 # number of demand (read+write) misses
+system.iocache.demand_misses::total 0 # number of demand (read+write) misses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_uncacheable_latency 1308159015940 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency 1308159015940 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 61327 # number of quiesce instructions executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 36142 # number of quiesce instructions executed
+
+---------- End Simulation Statistics ----------
--- /dev/null
+build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual FAILED!
[system]
type=LinuxArmSystem
-children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
-boot_loader=
-boot_loader_mem=Null
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
-flags_addr=0
-gic_cpu_addr=0
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
init_param=0
-kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-memories=system.physmem system.diskmem
+memories=system.nvmem system.physmem
midr_regval=890224640
physmem=system.physmem
readfile=tests/halt.sh
type=Bridge
delay=50000
filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:134217727
+filter_ranges_b=0:268435455
nack_delay=4000
req_size_a=16
req_size_b=16
side_a=system.iobus.port[0]
side_b=system.membus.port[0]
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
[system.cpu]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
[system.cpu.tracer]
type=ExeTracer
-[system.diskmem]
-type=PhysicalMemory
-file=/arm/scratch/sysexplr/dist/disks/ael-arm.ext2
-latency=30000
-latency_var=0
-null=false
-range=134217728:268435455
-zero=false
-port=system.membus.port[1]
-
[system.intrctrl]
type=IntrControl
sys=system
[system.iocache]
type=BaseCache
-addr_range=0:134217727
+addr_range=0:268435455
assoc=8
block_size=64
forward_snoops=false
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
warn_access=warn
pio=system.membus.default
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
[system.physmem]
type=PhysicalMemory
file=
type=RealView
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
+pci_cfg_base=0
system=system
[system.realview.a9scu]
VendorID=32902
config_latency=20000
ctrl_offset=2
-disks=
+disks=system.cf0
io_shift=1
max_backoff_delay=10000000
min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
+pci_bus=2
+pci_dev=7
pci_func=0
pio_latency=1000
platform=system.realview
pio_addr=268435456
pio_latency=1000
platform=system.realview
-proc_id=201326592
+proc_id0=201326592
+proc_id1=201327138
system=system
pio=system.iobus.port[2]
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-warn: instruction 'mcr bpiall' unimplemented
warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr bpiall' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiall' unimplemented
+warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: instruction 'mcr bpiall' unimplemented
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: instruction 'mcr bpiall' unimplemented
-warn: instruction 'mcr bpiall' unimplemented
-warn: instruction 'mcr bpiall' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 79074238500 because m5_exit instruction encountered
+Exiting @ tick 2503824454500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 0.079074 # Number of seconds simulated
-sim_ticks 79074238500 # Number of ticks simulated
+sim_seconds 2.503824 # Number of seconds simulated
+sim_ticks 2503824454500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94294 # Simulator instruction rate (inst/s)
-host_tick_rate 143722804 # Simulator tick rate (ticks/s)
-host_mem_usage 389860 # Number of bytes of host memory used
-host_seconds 550.19 # Real time elapsed on the host
-sim_insts 51879448 # Number of instructions simulated
-system.l2c.replacements 94945 # number of replacements
-system.l2c.tagsinuse 38237.402486 # Cycle average of tags in use
-system.l2c.total_refs 1052101 # Total number of references to valid blocks.
-system.l2c.sampled_refs 127394 # Sample count of references to valid blocks.
-system.l2c.avg_refs 8.258639 # Average number of references to valid blocks.
+host_inst_rate 79718 # Simulator instruction rate (inst/s)
+host_tick_rate 2598962996 # Simulator tick rate (ticks/s)
+host_mem_usage 429452 # Number of bytes of host memory used
+host_seconds 963.39 # Real time elapsed on the host
+sim_insts 76800038 # Number of instructions simulated
+system.l2c.replacements 119528 # number of replacements
+system.l2c.tagsinuse 25937.630096 # Cycle average of tags in use
+system.l2c.total_refs 1800987 # Total number of references to valid blocks.
+system.l2c.sampled_refs 150361 # Sample count of references to valid blocks.
+system.l2c.avg_refs 11.977754 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 6834.607637 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31402.794849 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.104288 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.479169 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 744764 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 111075 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 855839 # number of ReadReq hits
-system.l2c.Writeback_hits::0 435185 # number of Writeback hits
-system.l2c.Writeback_hits::total 435185 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 29 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 61163 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 61163 # number of ReadExReq hits
-system.l2c.demand_hits::0 805927 # number of demand (read+write) hits
-system.l2c.demand_hits::1 111075 # number of demand (read+write) hits
-system.l2c.demand_hits::total 917002 # number of demand (read+write) hits
-system.l2c.overall_hits::0 805927 # number of overall hits
-system.l2c.overall_hits::1 111075 # number of overall hits
-system.l2c.overall_hits::total 917002 # number of overall hits
-system.l2c.ReadReq_misses::0 21158 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 88 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21246 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 1695 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1695 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0 1 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0 107672 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 107672 # number of ReadExReq misses
-system.l2c.demand_misses::0 128830 # number of demand (read+write) misses
-system.l2c.demand_misses::1 88 # number of demand (read+write) misses
-system.l2c.demand_misses::total 128918 # number of demand (read+write) misses
-system.l2c.overall_misses::0 128830 # number of overall misses
-system.l2c.overall_misses::1 88 # number of overall misses
-system.l2c.overall_misses::total 128918 # number of overall misses
-system.l2c.ReadReq_miss_latency 1110312000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 5647552000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 6757864000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 6757864000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 765922 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 111163 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 877085 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 435185 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 435185 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 1724 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1724 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0 1 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 168835 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 168835 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 934757 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 111163 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1045920 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 934757 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 111163 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1045920 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.027624 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.000792 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.028416 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.983179 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.637735 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.137822 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.000792 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.138614 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.137822 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.000792 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.138614 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52477.171755 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 12617181.818182 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 12669658.989937 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 429.793510 # average UpgradeReq miss latency
+system.l2c.occ_blocks::0 11548.723381 # Average occupied blocks per context
+system.l2c.occ_blocks::1 14388.906715 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.176220 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.219557 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 1352767 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 155574 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1508341 # number of ReadReq hits
+system.l2c.Writeback_hits::0 630909 # number of Writeback hits
+system.l2c.Writeback_hits::total 630909 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 49 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0 19 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0 105993 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 105993 # number of ReadExReq hits
+system.l2c.demand_hits::0 1458760 # number of demand (read+write) hits
+system.l2c.demand_hits::1 155574 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1614334 # number of demand (read+write) hits
+system.l2c.overall_hits::0 1458760 # number of overall hits
+system.l2c.overall_hits::1 155574 # number of overall hits
+system.l2c.overall_hits::total 1614334 # number of overall hits
+system.l2c.ReadReq_misses::0 36107 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 150 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 36257 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 3257 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 3257 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0 9 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0 140403 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140403 # number of ReadExReq misses
+system.l2c.demand_misses::0 176510 # number of demand (read+write) misses
+system.l2c.demand_misses::1 150 # number of demand (read+write) misses
+system.l2c.demand_misses::total 176660 # number of demand (read+write) misses
+system.l2c.overall_misses::0 176510 # number of overall misses
+system.l2c.overall_misses::1 150 # number of overall misses
+system.l2c.overall_misses::total 176660 # number of overall misses
+system.l2c.ReadReq_miss_latency 1897665500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency 1154500 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency 52000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency 7382579000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency 9280244500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 9280244500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 1388874 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 155724 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1544598 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 630909 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 630909 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 3306 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 3306 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0 28 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 246396 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 246396 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 1635270 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 155724 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1790994 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 1635270 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 155724 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1790994 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.025997 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.000963 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.026961 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.985178 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0 0.321429 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.569827 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.107939 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.000963 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.108903 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.107939 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.000963 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.108903 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 52556.720304 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 12651103.333333 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 12703660.053637 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 354.467301 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52451.445130 # average ReadExReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::0 5777.777778 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52581.347977 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 52455.670263 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 76793909.090909 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 76846364.761172 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 52455.670263 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 76793909.090909 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 76846364.761172 # average overall miss latency
+system.l2c.demand_avg_miss_latency::0 52576.310124 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 61868296.666667 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 61920872.976791 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 52576.310124 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 61868296.666667 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 61920872.976791 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 87817 # number of writebacks
-system.l2c.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits 52 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 52 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 21194 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 1695 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses 1 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 107672 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 128866 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 128866 # number of overall MSHR misses
+system.l2c.writebacks 102659 # number of writebacks
+system.l2c.ReadReq_mshr_hits 99 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits 99 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 99 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses 36158 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 3257 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses 9 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 140403 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 176561 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 176561 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 848895000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 67801500 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency 40000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 4307970000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 5156865000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 5156865000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 28946635000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 749324446 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 29695959446 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.027671 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.190657 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.218328 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.983179 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_latency 1452283500 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 131732500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency 360000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5638732500 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 7091016000 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 7091016000 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 131768110500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 32345431294 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 164113541794 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.026034 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.232193 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.258227 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.985178 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.321429 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.637735 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 0.569827 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.137860 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.159253 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 1.297113 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.137860 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.159253 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 1.297113 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40053.552892 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.884956 # average UpgradeReq mshr miss latency
+system.l2c.demand_mshr_miss_rate::0 0.107971 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.133807 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 1.241778 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.107971 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.133807 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 1.241778 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40164.928923 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40445.962542 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40010.123338 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40017.265997 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40017.265997 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40161.054251 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40161.847747 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40161.847747 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25900550 # DTB read hits
-system.cpu.dtb.read_misses 64651 # DTB read misses
-system.cpu.dtb.write_hits 7192881 # DTB write hits
-system.cpu.dtb.write_misses 13036 # DTB write misses
+system.cpu.dtb.read_hits 51109554 # DTB read hits
+system.cpu.dtb.read_misses 89772 # DTB read misses
+system.cpu.dtb.write_hits 11994703 # DTB write hits
+system.cpu.dtb.write_misses 25525 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 2886 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 3633 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1097 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 8382 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 661 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25965201 # DTB read accesses
-system.cpu.dtb.write_accesses 7205917 # DTB write accesses
+system.cpu.dtb.perms_faults 2390 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51199326 # DTB read accesses
+system.cpu.dtb.write_accesses 12020228 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 33093431 # DTB hits
-system.cpu.dtb.misses 77687 # DTB misses
-system.cpu.dtb.accesses 33171118 # DTB accesses
-system.cpu.itb.inst_hits 6310237 # ITB inst hits
-system.cpu.itb.inst_misses 7717 # ITB inst misses
+system.cpu.dtb.hits 63104257 # DTB hits
+system.cpu.dtb.misses 115297 # DTB misses
+system.cpu.dtb.accesses 63219554 # DTB accesses
+system.cpu.itb.inst_hits 14358238 # ITB inst hits
+system.cpu.itb.inst_misses 11476 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 1666 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 2618 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 4317 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 8489 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 6317954 # ITB inst accesses
-system.cpu.itb.hits 6310237 # DTB hits
-system.cpu.itb.misses 7717 # DTB misses
-system.cpu.itb.accesses 6317954 # DTB accesses
-system.cpu.numCycles 158148478 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 14369714 # ITB inst accesses
+system.cpu.itb.hits 14358238 # DTB hits
+system.cpu.itb.misses 11476 # DTB misses
+system.cpu.itb.accesses 14369714 # DTB accesses
+system.cpu.numCycles 416612538 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 12403718 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 10473693 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 647177 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11077874 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8725285 # Number of BTB hits
+system.cpu.BPredUnit.lookups 16387222 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12668617 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1109677 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 14122008 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 10400042 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 825346 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 148570 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 15848399 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 58464536 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 12403718 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9550631 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 15311451 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2844155 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 92931 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 55530026 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 15278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 87268 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 242 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 6305391 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 273417 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4478 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 88893250 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.826227 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.063220 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1438387 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 228434 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 33205064 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 105935094 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16387222 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11838429 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24790129 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 7281806 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 140399 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 92648607 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 1264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 149325 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 219222 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 315 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 14348946 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1053874 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6421 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 156122024 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.843787 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.188312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 73600633 82.80% 82.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1267818 1.43% 84.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1758600 1.98% 86.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1303689 1.47% 87.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4624910 5.20% 92.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 783016 0.88% 93.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 755228 0.85% 94.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 591057 0.66% 95.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4208299 4.73% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 131359328 84.14% 84.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1797067 1.15% 85.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2650142 1.70% 86.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3706376 2.37% 89.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2183779 1.40% 90.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1469088 0.94% 91.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2676851 1.71% 93.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 859477 0.55% 93.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9419916 6.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 88893250 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.078431 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.369681 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17889712 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 54159673 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 13693957 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1214512 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1935396 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1196991 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 73836 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 71078898 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 241088 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1935396 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 19399410 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 33418578 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 16504909 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 12375675 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5259282 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 68683031 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 458239 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 182953 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2809051 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 70419738 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 296318415 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 296251688 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 66727 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 51890716 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 18529021 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 807343 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 660120 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 14009466 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 11753719 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8138684 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 887625 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1407204 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 61880073 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4035866 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 76596153 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 165478 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 13504163 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 24143581 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1073057 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 88893250 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.861664 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.427794 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 156122024 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.039334 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.254277 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35461706 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 92496954 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22296946 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1073972 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4792446 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2336165 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 178310 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 123347211 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 575607 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4792446 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37647350 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36719045 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 49837786 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21186830 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5938567 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 115130197 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4438 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 893530 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3968160 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 43280 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 119684467 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 529404061 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529305097 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 98964 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 77501999 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 42182467 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1209283 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1098761 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12191274 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 22237858 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14288032 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2207613 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2740072 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 103897694 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1876028 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126150518 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 258491 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 28028723 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 75807996 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 377489 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 156122024 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.808025 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.494664 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 55657719 62.61% 62.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14175743 15.95% 78.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 6670691 7.50% 86.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4258110 4.79% 90.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5767054 6.49% 97.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1381276 1.55% 98.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 654272 0.74% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 222610 0.25% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 105775 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 109310496 70.02% 70.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15452280 9.90% 79.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7704093 4.93% 84.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6547773 4.19% 89.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12500649 8.01% 97.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2674638 1.71% 98.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1385356 0.89% 99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 415101 0.27% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 131638 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 88893250 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 156122024 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 28225 0.64% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 1 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 4144387 93.61% 94.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 254758 5.75% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 45842 0.53% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 8 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8169590 94.68% 95.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 412814 4.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2393223 3.12% 3.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 39796206 51.96% 55.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 68882 0.09% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 1 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 880 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 55.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26733019 34.90% 90.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7603891 9.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 60408589 47.89% 47.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 96901 0.08% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 3 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2257 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52851212 41.90% 89.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12685017 10.06% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 76596153 # Type of FU issued
-system.cpu.iq.rate 0.484331 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 4427371 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.057801 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 246739451 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 79485386 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 59144129 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 16089 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9683 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 6534 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 78621825 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 8476 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 479578 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126150518 # Type of FU issued
+system.cpu.iq.rate 0.302801 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8628254 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.068397 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 417401182 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 133881929 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87720713 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23251 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13846 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10518 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 134660044 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12198 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 599778 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2574412 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7673 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 75993 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1060962 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6553966 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11010 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 95494 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2507321 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 15898252 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 9806 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 32840687 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1141901 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1935396 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 21193831 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 271998 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 66089327 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 340309 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 11753719 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 8138684 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4003938 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 14746 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 54897 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 75993 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 528463 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 171712 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 700175 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 75657925 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 26402371 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 938228 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4792446 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28191284 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 424606 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 105991714 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 477393 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 22237858 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 14288032 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1227462 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 89856 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 7011 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 95494 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 852380 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 256698 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1109078 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 122676478 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51808342 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3474040 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 173388 # number of nop insts executed
-system.cpu.iew.exec_refs 33905993 # number of memory reference insts executed
-system.cpu.iew.exec_branches 10120483 # Number of branches executed
-system.cpu.iew.exec_stores 7503622 # Number of stores executed
-system.cpu.iew.exec_rate 0.478398 # Inst execution rate
-system.cpu.iew.wb_sent 75261887 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 59150663 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 31134340 # num instructions producing a value
-system.cpu.iew.wb_consumers 55908801 # num instructions consuming a value
+system.cpu.iew.exec_nop 217992 # number of nop insts executed
+system.cpu.iew.exec_refs 64319690 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11745709 # Number of branches executed
+system.cpu.iew.exec_stores 12511348 # Number of stores executed
+system.cpu.iew.exec_rate 0.294462 # Inst execution rate
+system.cpu.iew.wb_sent 120986716 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87731231 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47245202 # num instructions producing a value
+system.cpu.iew.wb_consumers 86878076 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.374020 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.556877 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.210582 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.543810 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 52002678 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 11830112 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 2962809 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 620839 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 86957882 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.598021 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.499250 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 76950419 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 28805793 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1498539 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 978025 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 151411950 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.508219 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.450093 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 67332100 77.43% 77.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 9518451 10.95% 88.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 2434571 2.80% 91.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1362976 1.57% 92.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3331765 3.83% 96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 735683 0.85% 97.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 547610 0.63% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 322786 0.37% 98.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1371940 1.58% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 122345277 80.80% 80.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 15024261 9.92% 90.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4072409 2.69% 93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2238793 1.48% 94.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1805162 1.19% 96.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1472326 0.97% 97.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1253236 0.83% 97.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 640621 0.42% 98.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2559865 1.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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+system.cpu.dcache.LoadLockedReq_accesses::0 313583 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 313583 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0 285555 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 285555 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0 25501561 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15256946 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 15256946 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::total 25501561 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0 25501561 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15256946 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.058102 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.306957 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060108 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::0 0.000010 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.166781 # miss rate for demand accesses
+system.cpu.dcache.overall_accesses::total 25501561 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.047514 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.289960 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043080 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::0 0.000102 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.144799 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.166781 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0 0.144799 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14604.668139 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15009.100232 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 39792.790272 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 37173.142514 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15091.842900 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16228.403287 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 55000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0 26862.068966 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 34850.136434 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 32818.617266 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 34850.136434 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 32818.617266 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 8903490 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 871500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1190 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 31 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7481.924370 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 28112.903226 # average number of cycles each access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 16440438 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 7572500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2965 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5544.835750 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26757.950530 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 392115 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 249191 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 1874723 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 1026 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 2123914 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 2123914 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 250130 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 170532 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 5594 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses 1 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 420662 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 420662 # number of overall MSHR misses
+system.cpu.dcache.writebacks 573108 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 338981 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 2717547 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 3056528 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 3056528 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 386495 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 249568 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses 12056 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses 29 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 636063 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 636063 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3343532500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 6556670490 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66421000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 52000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 9900202990 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 9900202990 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199457500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 947259668 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 39146717168 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.029105 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency 5252112000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 8923093438 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161656000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 684500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 14175205438 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 14175205438 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147157433500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42270831280 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 189428264780 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025313 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025594 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024389 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050792 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000010 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000102 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.027572 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::0 0.024942 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.027572 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0.024942 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13367.179067 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38448.329287 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.614587 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 52000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23534.816527 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23534.816527 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13589.081359 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35754.156935 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13408.759124 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 23603.448276 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22285.851304 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22285.851304 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency 1308136733935 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency 1308136733935 # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88013 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
+++ /dev/null
-build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 FAILED!
--- /dev/null
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
+boot_cpu_frequency=500
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
+init_param=0
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+load_addr_mask=268435455
+machine_type=RealView_PBX
+mem_mode=atomic
+memories=system.nvmem system.physmem
+midr_regval=890224640
+physmem=system.physmem
+readfile=tests/halt.sh
+symbolfile=
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+work_end_ckpt_count=0
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+work_item_id=-1
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:268435455
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts itb tracer
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+itb=system.cpu0.itb
+max_insts_all_threads=0
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+max_loads_any_thread=0
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+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
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+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[4]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
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+prefetch_latency=10000
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+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[3]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts itb tracer
+checker=Null
+clock=500
+cpu_id=1
+defer_registration=false
+do_checkpoint_insts=true
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+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+itb=system.cpu1.itb
+max_insts_all_threads=0
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+phase=0
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+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu1.tracer
+width=1
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
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+prefetcher_size=100
+prioritizeRequests=false
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+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[8]
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.toL2Bus.port[7]
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:268435455
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+is_top_level=false
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[25]
+mem_side=system.membus.port[7]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=2
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[8]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.realview
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=true
+port=system.membus.port[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268451840
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=1000
+platform=system.realview
+system=system
+config=system.iobus.port[26]
+dma=system.iobus.port[27]
+pio=system.iobus.port[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=41667
+gic=system.realview.gic
+int_num=55
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pio_addr=268566528
+pio_latency=10000
+platform=system.realview
+system=system
+vnc=system.vncserver
+dma=system.iobus.port[28]
+pio=system.iobus.port[5]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268632064
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+fake_mem=true
+pio_addr=1073741824
+pio_latency=1000
+pio_size=536870912
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[24]
+
+[system.realview.gic]
+type=Gic
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.port[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268513280
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268517376
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268521472
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+fake_mem=false
+pio_addr=520101888
+pio_latency=1000
+pio_size=4095
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.port[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268455936
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[22]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+idreg=0
+pio_addr=268435456
+pio_latency=1000
+platform=system.realview
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.port[2]
+
+[system.realview.rtc_fake]
+type=AmbaFake
+amba_id=266289
+ignore_access=false
+pio_addr=268529664
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268492800
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=269357056
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=true
+pio_addr=268439552
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268488704
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[3]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[4]
+
+[system.realview.uart]
+type=Pl011
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=1000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.port[1]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268476416
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268480512
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268484608
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268500992
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+number=0
+port=5900
+
--- /dev/null
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr dccimvac' unimplemented
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
+warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 2411694099500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.411694 # Number of seconds simulated
+sim_ticks 2411694099500 # Number of ticks simulated
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1186264 # Simulator instruction rate (inst/s)
+host_tick_rate 35957520604 # Simulator tick rate (ticks/s)
+host_mem_usage 417168 # Number of bytes of host memory used
+host_seconds 67.07 # Real time elapsed on the host
+sim_insts 79563488 # Number of instructions simulated
+system.l2c.replacements 127720 # number of replacements
+system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use
+system.l2c.total_refs 1498989 # Total number of references to valid blocks.
+system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
+system.l2c.avg_refs 9.600780 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context
+system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context
+system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits
+system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits
+system.l2c.Writeback_hits::0 580461 # number of Writeback hits
+system.l2c.Writeback_hits::total 580461 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits
+system.l2c.demand_hits::0 771021 # number of demand (read+write) hits
+system.l2c.demand_hits::1 537612 # number of demand (read+write) hits
+system.l2c.demand_hits::2 12920 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits
+system.l2c.overall_hits::0 771021 # number of overall hits
+system.l2c.overall_hits::1 537612 # number of overall hits
+system.l2c.overall_hits::2 12920 # number of overall hits
+system.l2c.overall_hits::total 1321553 # number of overall hits
+system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses
+system.l2c.ReadReq_misses::2 52 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses
+system.l2c.demand_misses::0 118723 # number of demand (read+write) misses
+system.l2c.demand_misses::1 64009 # number of demand (read+write) misses
+system.l2c.demand_misses::2 52 # number of demand (read+write) misses
+system.l2c.demand_misses::total 182784 # number of demand (read+write) misses
+system.l2c.overall_misses::0 118723 # number of overall misses
+system.l2c.overall_misses::1 64009 # number of overall misses
+system.l2c.overall_misses::2 52 # number of overall misses
+system.l2c.overall_misses::total 182784 # number of overall misses
+system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 0 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses
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+system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses
+system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 111818 # number of writebacks
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
+system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 9339288 # DTB read hits
+system.cpu0.dtb.read_misses 5153 # DTB read misses
+system.cpu0.dtb.write_hits 6907876 # DTB write hits
+system.cpu0.dtb.write_misses 1048 # DTB write misses
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+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9344441 # DTB read accesses
+system.cpu0.dtb.write_accesses 6908924 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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+system.cpu0.dtb.misses 6201 # DTB misses
+system.cpu0.dtb.accesses 16253365 # DTB accesses
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+system.cpu0.itb.inst_misses 2978 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses
+system.cpu0.itb.hits 34822552 # DTB hits
+system.cpu0.itb.misses 2978 # DTB misses
+system.cpu0.itb.accesses 34825530 # DTB accesses
+system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.num_insts 44975797 # Number of instructions executed
+system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
+system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 39858123 # number of integer instructions
+system.cpu0.num_fp_insts 4945 # number of float instructions
+system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written
+system.cpu0.num_mem_refs 17030946 # number of memory refs
+system.cpu0.num_load_insts 9786549 # Number of load instructions
+system.cpu0.num_store_insts 7244397 # Number of store instructions
+system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles
+system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed
+system.cpu0.icache.replacements 504460 # number of replacements
+system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use
+system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::0 34319155 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits
+system.cpu0.icache.demand_hits::0 34319155 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::1 0 # number of overall hits
+system.cpu0.icache.overall_hits::total 34319155 # number of overall hits
+system.cpu0.icache.ReadReq_misses::0 504973 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses
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+system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::1 0 # number of overall misses
+system.cpu0.icache.overall_misses::total 504973 # number of overall misses
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+system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::0 0.014501 # miss rate for ReadReq accesses
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+system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::0 0.014501 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.writebacks 24728 # number of writebacks
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+system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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+system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.replacements 380107 # number of replacements
+system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0 479.716402 # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0 0.936946 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::0 7803296 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::0 6534059 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0 172314 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::0 174866 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits
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+system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::0 237350 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::0 183580 # number of WriteReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::0 9878 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::0 7293 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses
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+system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::1 0 # number of overall misses
+system.cpu0.dcache.overall_misses::total 420930 # number of overall misses
+system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::0 8040646 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::0 182192 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::0 182159 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::0 14758285 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::0 0.029519 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::0 0.027328 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.054218 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.040036 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::0 0.028522 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
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+system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written
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+system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
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+system.iocache.avg_refs no_value # Average number of references to valid blocks.
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.iocache.demand_misses::1 0 # number of demand (read+write) misses
+system.iocache.demand_misses::total 0 # number of demand (read+write) misses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
[system]
type=LinuxArmSystem
-children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
-boot_loader=
-boot_loader_mem=Null
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
-flags_addr=0
-gic_cpu_addr=0
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
-midr_regval=890236928
+memories=system.nvmem system.physmem
+midr_regval=890224640
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
type=Bridge
delay=50000
filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:134217727
+filter_ranges_b=0:268435455
nack_delay=4000
req_size_a=16
req_size_b=16
side_a=system.iobus.port[0]
side_b=system.membus.port[0]
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
[system.cpu]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts itb tracer
[system.cpu.tracer]
type=ExeTracer
-[system.diskmem]
-type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
-latency=30000
-latency_var=0
-null=false
-range=134217728:268435455
-zero=false
-port=system.membus.port[1]
-
[system.intrctrl]
type=IntrControl
sys=system
[system.iocache]
type=BaseCache
-addr_range=0:134217727
+addr_range=0:268435455
assoc=8
block_size=64
forward_snoops=false
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.l2c]
type=BaseCache
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[7]
+mem_side=system.membus.port[8]
[system.membus]
type=Bus
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
warn_access=warn
pio=system.membus.default
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
[system.physmem]
type=PhysicalMemory
file=
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
+pci_cfg_base=0
system=system
[system.realview.a9scu]
VendorID=32902
config_latency=20000
ctrl_offset=2
-disks=
+disks=system.cf0
io_shift=1
max_backoff_delay=10000000
min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
+pci_bus=2
+pci_dev=7
pci_func=0
pio_latency=1000
platform=system.realview
[system.realview.flash_fake]
type=IsaFake
+fake_mem=true
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
[system.realview.l2x0_fake]
type=IsaFake
+fake_mem=false
pio_addr=520101888
pio_latency=1000
pio_size=4095
warn_access=
pio=system.membus.port[4]
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
-proc_id=201326592
+proc_id0=201326592
+proc_id1=201327138
system=system
pio=system.iobus.port[2]
warn: Sockets disabled, not accepting vnc client connections
-For more information see: http://www.m5sim.org/warn/af6a84f6
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: The clidr register always reports 0 caches.
-For more information see: http://www.m5sim.org/warn/23a3c326
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
-For more information see: http://www.m5sim.org/warn/2c4acb9c
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr icimvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-For more information see: http://www.m5sim.org/warn/7998f2ea
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 2 2011 15:06:32
-M5 started May 2 2011 15:06:36
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 26344863500 because m5_exit instruction encountered
+Exiting @ tick 2332316587000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 2945797 # Simulator instruction rate (inst/s)
-host_mem_usage 382504 # Number of bytes of host memory used
-host_seconds 17.65 # Real time elapsed on the host
-host_tick_rate 1493029395 # Simulator tick rate (ticks/s)
+sim_seconds 2.332317 # Number of seconds simulated
+sim_ticks 2332316587000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51978646 # Number of instructions simulated
-sim_seconds 0.026345 # Number of seconds simulated
-sim_ticks 26344863500 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 95328 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0 7808976 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7808976 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 7572677 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7572677 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.030260 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 236299 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 236299 # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6664019 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6664019 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 6491936 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6491936 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.025823 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 172083 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 172083 # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.645976 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14472995 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14472995 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 14064613 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14064613 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028217 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 408382 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 408382 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 511.736581 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999486 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0 14472995 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 14472995 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 14064613 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 14064613 # number of overall hits
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.028217 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 408382 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 408382 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 411144 # number of replacements
-system.cpu.dcache.sampled_refs 411656 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.736581 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14262224 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 380291 # number of writebacks
-system.cpu.dtb.accesses 15497629 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 2239 # Number of entries that have been flushed from TLB
+host_inst_rate 1407778 # Simulator instruction rate (inst/s)
+host_tick_rate 42901571145 # Simulator tick rate (ticks/s)
+host_mem_usage 417476 # Number of bytes of host memory used
+host_seconds 54.36 # Real time elapsed on the host
+sim_insts 76532931 # Number of instructions simulated
+system.l2c.replacements 116822 # number of replacements
+system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use
+system.l2c.total_refs 1520830 # Total number of references to valid blocks.
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+system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context
+system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy
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+system.l2c.Writeback_hits::0 604613 # number of Writeback hits
+system.l2c.Writeback_hits::total 604613 # number of Writeback hits
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+system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
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+system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses
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+system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses)
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+system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
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+system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
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+system.cpu.dtb.read_misses 7288 # DTB read misses
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+system.cpu.dtb.write_misses 2199 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15491993 # DTB hits
+system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5636 # DTB misses
-system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 787 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8721338 # DTB read accesses
-system.cpu.dtb.read_hits 8716687 # DTB read hits
-system.cpu.dtb.read_misses 4651 # DTB read misses
-system.cpu.dtb.write_accesses 6776291 # DTB write accesses
-system.cpu.dtb.write_hits 6775306 # DTB write hits
-system.cpu.dtb.write_misses 985 # DTB write misses
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-system.cpu.icache.ReadReq_hits::0 41024796 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 41024796 # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses::0 432196 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 432196 # number of ReadReq misses
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-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu.icache.demand_accesses::0 41456992 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 41456992 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 41024796 # number of demand (read+write) hits
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+system.cpu.dtb.accesses 26148258 # DTB accesses
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+system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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+system.cpu.itb.inst_accesses 60278360 # ITB inst accesses
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+system.cpu.itb.misses 4471 # DTB misses
+system.cpu.itb.accesses 60278360 # DTB accesses
+system.cpu.numCycles 4664556206 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 76532931 # Number of instructions executed
+system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses
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+system.cpu.num_func_calls 1971944 # number of times a function call or return occured
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+system.cpu.num_fp_insts 10269 # number of float instructions
+system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read
+system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
+system.cpu.num_mem_refs 27310784 # number of memory refs
+system.cpu.num_load_insts 15607074 # Number of load instructions
+system.cpu.num_store_insts 11703710 # Number of store instructions
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+system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles
+system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
+system.cpu.icache.replacements 847054 # number of replacements
+system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
+system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits
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system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 41024796 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 59429083 # number of overall hits
+system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
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system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 432196 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 432196 # number of demand (read+write) misses
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-system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
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-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 476.343594 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.930359 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0 41456992 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 41456992 # number of overall (read+write) accesses
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+system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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+system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 41024796 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
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-system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 432196 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 432196 # number of overall misses
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 44721 # number of writebacks
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 431683 # number of replacements
-system.cpu.icache.sampled_refs 432195 # Sample count of references to valid blocks.
+system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 476.343594 # Cycle average of tags in use
-system.cpu.icache.total_refs 41024796 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 4572561500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 33762 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41458119 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41455189 # DTB hits
-system.cpu.itb.inst_accesses 41458119 # ITB inst accesses
-system.cpu.itb.inst_hits 41455189 # ITB inst hits
-system.cpu.itb.inst_misses 2930 # ITB inst misses
-system.cpu.itb.misses 2930 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 52689728 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 52689728 # Number of busy cycles
-system.cpu.num_conditional_control_insts 7011782 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
-system.cpu.num_fp_insts 6058 # number of float instructions
-system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
-system.cpu.num_func_calls 1108496 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 51978646 # Number of instructions executed
-system.cpu.num_int_alu_accesses 42407849 # Number of integer alu accesses
-system.cpu.num_int_insts 42407849 # number of integer instructions
-system.cpu.num_int_register_reads 222699258 # number of times the integer registers were read
-system.cpu.num_int_register_writes 49674551 # number of times the integer registers were written
-system.cpu.num_load_insts 9176676 # Number of load instructions
-system.cpu.num_mem_refs 16251075 # number of memory refs
-system.cpu.num_store_insts 7074399 # Number of store instructions
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 622134 # number of replacements
+system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
+system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0 23093997 # number of overall hits
+system.cpu.dcache.overall_hits::1 0 # number of overall hits
+system.cpu.dcache.overall_hits::total 23093997 # number of overall hits
+system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses
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+system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0 614445 # number of overall misses
+system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::total 614445 # number of overall misses
+system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses
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+system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 559892 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 0 # number of replacements
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 170242 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 170242 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0 60575 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 60575 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0 0.644183 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 109667 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 109667 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 671513 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 7076 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 678589 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 650281 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 7045 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 657326 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.031618 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.004381 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.035999 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 21232 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 31 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21263 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 1841 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1841 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0 0.989680 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 414053 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 414053 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 414053 # number of Writeback hits
-system.l2c.Writeback_hits::total 414053 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 6.728889 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 841755 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 7076 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 848831 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 710856 # number of demand (read+write) hits
-system.l2c.demand_hits::1 7045 # number of demand (read+write) hits
-system.l2c.demand_hits::total 717901 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.155507 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.004381 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.159888 # miss rate for demand accesses
-system.l2c.demand_misses::0 130899 # number of demand (read+write) misses
-system.l2c.demand_misses::1 31 # number of demand (read+write) misses
-system.l2c.demand_misses::total 130930 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 5062.983429 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31189.392245 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.077255 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.475912 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 841755 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 7076 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 848831 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 710856 # number of overall hits
-system.l2c.overall_hits::1 7045 # number of overall hits
-system.l2c.overall_hits::total 717901 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.155507 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.004381 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.159888 # miss rate for overall accesses
-system.l2c.overall_misses::0 130899 # number of overall misses
-system.l2c.overall_misses::1 31 # number of overall misses
-system.l2c.overall_misses::total 130930 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 97110 # number of replacements
-system.l2c.sampled_refs 129685 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36252.375674 # Cycle average of tags in use
-system.l2c.total_refs 872636 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 91105 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
-build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
--- /dev/null
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
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+boot_cpu_frequency=500
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+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
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+load_addr_mask=268435455
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+symbolfile=
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+
+[system.bridge]
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+
+[system.cf0]
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+
+[system.cf0.image]
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+
+[system.cf0.image.child]
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+read_only=true
+
+[system.cpu0]
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+
+[system.cpu0.dcache]
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+
+[system.cpu0.dtb]
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+
+[system.cpu0.dtb.walker]
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+
+[system.cpu0.icache]
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+
+[system.cpu0.interrupts]
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+
+[system.cpu0.itb]
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+
+[system.cpu0.itb.walker]
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+
+[system.cpu0.tracer]
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+
+[system.cpu1]
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+
+[system.cpu1.dcache]
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+
+[system.cpu1.dtb]
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+
+[system.cpu1.dtb.walker]
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+
+[system.cpu1.icache]
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+
+[system.cpu1.interrupts]
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+
+[system.cpu1.itb]
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+
+[system.cpu1.itb.walker]
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+
+[system.cpu1.tracer]
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+
+[system.intrctrl]
+type=IntrControl
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+
+[system.iobus]
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+clock=1000
+header_cycles=1
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+port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
+
+[system.iocache]
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+
+[system.l2c]
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+size=4194304
+subblock_size=0
+tgts_per_mshr=16
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+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[8]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+fake_mem=false
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.realview
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=true
+port=system.membus.port[2]
+
+[system.realview]
+type=RealView
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+intrctrl=system.intrctrl
+pci_cfg_base=0
+system=system
+
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268451840
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[21]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=402653184
+BAR0LegacyIO=true
+BAR0Size=16
+BAR1=402653440
+BAR1LegacyIO=true
+BAR1Size=1
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=2
+disks=system.cf0
+io_shift=1
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=2
+pci_dev=7
+pci_func=0
+pio_latency=1000
+platform=system.realview
+system=system
+config=system.iobus.port[26]
+dma=system.iobus.port[27]
+pio=system.iobus.port[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=41667
+gic=system.realview.gic
+int_num=55
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pio_addr=268566528
+pio_latency=10000
+platform=system.realview
+system=system
+vnc=system.vncserver
+dma=system.iobus.port[28]
+pio=system.iobus.port[5]
+
+[system.realview.dmac_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268632064
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[9]
+
+[system.realview.flash_fake]
+type=IsaFake
+fake_mem=true
+pio_addr=1073741824
+pio_latency=1000
+pio_size=536870912
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[24]
+
+[system.realview.gic]
+type=Gic
+cpu_addr=520093952
+cpu_pio_delay=10000
+dist_addr=520097792
+dist_pio_delay=10000
+int_latency=10000
+it_lines=128
+platform=system.realview
+system=system
+pio=system.membus.port[3]
+
+[system.realview.gpio0_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268513280
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[16]
+
+[system.realview.gpio1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268517376
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[17]
+
+[system.realview.gpio2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268521472
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[18]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=52
+is_mouse=false
+pio_addr=268460032
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=1000000
+int_num=53
+is_mouse=true
+pio_addr=268464128
+pio_latency=1000
+platform=system.realview
+system=system
+vnc=system.vncserver
+pio=system.iobus.port[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+fake_mem=false
+pio_addr=520101888
+pio_latency=1000
+pio_size=4095
+platform=system.realview
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.port[4]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268455936
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[22]
+
+[system.realview.realview_io]
+type=RealViewCtrl
+idreg=0
+pio_addr=268435456
+pio_latency=1000
+platform=system.realview
+proc_id0=201326592
+proc_id1=201327138
+system=system
+pio=system.iobus.port[2]
+
+[system.realview.rtc_fake]
+type=AmbaFake
+amba_id=266289
+ignore_access=false
+pio_addr=268529664
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[23]
+
+[system.realview.sci_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268492800
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[20]
+
+[system.realview.smc_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=269357056
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[13]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=true
+pio_addr=268439552
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[14]
+
+[system.realview.ssp_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268488704
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[19]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=36
+int_num1=36
+pio_addr=268505088
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[3]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clock0=1000000
+clock1=1000000
+gic=system.realview.gic
+int_num0=37
+int_num1=37
+pio_addr=268509184
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[4]
+
+[system.realview.uart]
+type=Pl011
+end_on_eot=false
+gic=system.realview.gic
+int_delay=100000
+int_num=44
+pio_addr=268472320
+pio_latency=1000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.port[1]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268476416
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[10]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268480512
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[11]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268484608
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[12]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+ignore_access=false
+pio_addr=268500992
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.iobus.port[15]
+
+[system.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+number=0
+port=5900
+
--- /dev/null
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: The clidr register always reports 0 caches.
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
+warn: The csselr register isn't implemented.
+warn: The ccsidr register isn't implemented and always reads as 0.
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr dccimvac' unimplemented
+warn: instruction 'mcr dccmvau' unimplemented
+warn: instruction 'mcr icimvau' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
+warn: LCD dual screen mode not supported
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
+hack: be nice to actually delete the event here
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 2669611225000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.669611 # Number of seconds simulated
+sim_ticks 2669611225000 # Number of ticks simulated
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 491804 # Simulator instruction rate (inst/s)
+host_tick_rate 16743499108 # Simulator tick rate (ticks/s)
+host_mem_usage 418920 # Number of bytes of host memory used
+host_seconds 159.44 # Real time elapsed on the host
+sim_insts 78413959 # Number of instructions simulated
+system.l2c.replacements 127749 # number of replacements
+system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use
+system.l2c.total_refs 1540412 # Total number of references to valid blocks.
+system.l2c.sampled_refs 157158 # Sample count of references to valid blocks.
+system.l2c.avg_refs 9.801677 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context
+system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context
+system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits
+system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits
+system.l2c.Writeback_hits::0 589400 # number of Writeback hits
+system.l2c.Writeback_hits::total 589400 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 1143 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 692 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0 168 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1 186 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0 42506 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 58554 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits
+system.l2c.demand_hits::0 605365 # number of demand (read+write) hits
+system.l2c.demand_hits::1 714697 # number of demand (read+write) hits
+system.l2c.demand_hits::2 11798 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits
+system.l2c.overall_hits::0 605365 # number of overall hits
+system.l2c.overall_hits::1 714697 # number of overall hits
+system.l2c.overall_hits::2 11798 # number of overall hits
+system.l2c.overall_hits::total 1331860 # number of overall hits
+system.l2c.ReadReq_misses::0 18655 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 16034 # number of ReadReq misses
+system.l2c.ReadReq_misses::2 50 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses
+system.l2c.demand_misses::0 115979 # number of demand (read+write) misses
+system.l2c.demand_misses::1 67558 # number of demand (read+write) misses
+system.l2c.demand_misses::2 50 # number of demand (read+write) misses
+system.l2c.demand_misses::total 183587 # number of demand (read+write) misses
+system.l2c.overall_misses::0 115979 # number of overall misses
+system.l2c.overall_misses::1 67558 # number of overall misses
+system.l2c.overall_misses::2 50 # number of overall misses
+system.l2c.overall_misses::total 183587 # number of overall misses
+system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses
+system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses
+system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses
+system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses
+system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 111955 # number of writebacks
+system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 9 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 7857580 # DTB read hits
+system.cpu0.dtb.read_misses 1898 # DTB read misses
+system.cpu0.dtb.write_hits 6224259 # DTB write hits
+system.cpu0.dtb.write_misses 1143 # DTB write misses
+system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7859478 # DTB read accesses
+system.cpu0.dtb.write_accesses 6225402 # DTB write accesses
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+system.cpu0.dtb.hits 14081839 # DTB hits
+system.cpu0.dtb.misses 3041 # DTB misses
+system.cpu0.dtb.accesses 14084880 # DTB accesses
+system.cpu0.itb.inst_hits 35747911 # ITB inst hits
+system.cpu0.itb.inst_misses 1204 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses
+system.cpu0.itb.hits 35747911 # DTB hits
+system.cpu0.itb.misses 1204 # DTB misses
+system.cpu0.itb.accesses 35749115 # DTB accesses
+system.cpu0.numCycles 5337805216 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.num_insts 43969024 # Number of instructions executed
+system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses
+system.cpu0.num_func_calls 977479 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4512711 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 39881498 # number of integer instructions
+system.cpu0.num_fp_insts 4107 # number of float instructions
+system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written
+system.cpu0.num_mem_refs 14677999 # number of memory refs
+system.cpu0.num_load_insts 8148547 # Number of load instructions
+system.cpu0.num_store_insts 6529452 # Number of store instructions
+system.cpu0.num_idle_cycles 5107410781.564784 # Number of idle cycles
+system.cpu0.num_busy_cycles 230394434.435216 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed
+system.cpu0.icache.replacements 380069 # number of replacements
+system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use
+system.cpu0.icache.total_refs 35367311 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits
+system.cpu0.icache.demand_hits::0 35367311 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::1 0 # number of overall hits
+system.cpu0.icache.overall_hits::total 35367311 # number of overall hits
+system.cpu0.icache.ReadReq_misses::0 380583 # number of ReadReq misses
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+system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::1 0 # number of overall misses
+system.cpu0.icache.overall_misses::total 380583 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency 5651439000 # number of demand (read+write) miss cycles
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+system.cpu0.icache.ReadReq_accesses::0 35747894 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::0 35747894 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses
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+system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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+system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.writebacks 12960 # number of writebacks
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+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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+system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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+system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.replacements 334596 # number of replacements
+system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy
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+system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits
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+system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses
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+system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::0 372868 # number of overall misses
+system.cpu0.dcache.overall_misses::1 0 # number of overall misses
+system.cpu0.dcache.overall_misses::total 372868 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles
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+system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles
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+system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks 294891 # number of writebacks
+system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 7762496 # DTB read hits
+system.cpu1.dtb.read_misses 5432 # DTB read misses
+system.cpu1.dtb.write_hits 5411648 # DTB write hits
+system.cpu1.dtb.write_misses 1096 # DTB write misses
+system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 7767928 # DTB read accesses
+system.cpu1.dtb.write_accesses 5412744 # DTB write accesses
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+system.cpu1.dtb.hits 13174144 # DTB hits
+system.cpu1.dtb.misses 6528 # DTB misses
+system.cpu1.dtb.accesses 13180672 # DTB accesses
+system.cpu1.itb.inst_hits 26848280 # ITB inst hits
+system.cpu1.itb.inst_misses 3154 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
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+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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+system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB
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+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 26851434 # ITB inst accesses
+system.cpu1.itb.hits 26848280 # DTB hits
+system.cpu1.itb.misses 3154 # DTB misses
+system.cpu1.itb.accesses 26851434 # DTB accesses
+system.cpu1.numCycles 5339222450 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.num_insts 34444935 # Number of instructions executed
+system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses
+system.cpu1.num_func_calls 1093852 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3362553 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 31033253 # number of integer instructions
+system.cpu1.num_fp_insts 5714 # number of float instructions
+system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 32585304 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written
+system.cpu1.num_mem_refs 13796843 # number of memory refs
+system.cpu1.num_load_insts 8139019 # Number of load instructions
+system.cpu1.num_store_insts 5657824 # Number of store instructions
+system.cpu1.num_idle_cycles 4950307250.068146 # Number of idle cycles
+system.cpu1.num_busy_cycles 388915199.931854 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed
+system.cpu1.icache.replacements 508221 # number of replacements
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+system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy
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+system.cpu1.icache.overall_hits::1 0 # number of overall hits
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+system.cpu1.icache.overall_misses::1 0 # number of overall misses
+system.cpu1.icache.overall_misses::total 508733 # number of overall misses
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+system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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+system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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+system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
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+system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.writebacks 27998 # number of writebacks
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+system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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+system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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+system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.replacements 295754 # number of replacements
+system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 11737107 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context
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+system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits
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+system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits
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+system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits
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+system.cpu1.dcache.overall_hits::1 0 # number of overall hits
+system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits
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+system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses
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+system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses
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+system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses
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+system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 325738 # number of overall misses
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+system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses
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+system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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+system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks 253551 # number of writebacks
+system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.avg_refs no_value # Average number of references to valid blocks.
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.demand_hits::0 0 # number of demand (read+write) hits
+system.iocache.demand_hits::1 0 # number of demand (read+write) hits
+system.iocache.demand_hits::total 0 # number of demand (read+write) hits
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
+system.iocache.demand_misses::0 0 # number of demand (read+write) misses
+system.iocache.demand_misses::1 0 # number of demand (read+write) misses
+system.iocache.demand_misses::total 0 # number of demand (read+write) misses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
--- /dev/null
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
[system]
type=LinuxArmSystem
-children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
-boot_loader=
-boot_loader_mem=Null
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
-flags_addr=0
-gic_cpu_addr=0
+boot_loader=/chips/pd/randd/dist/binaries/boot.arm
+boot_loader_mem=system.nvmem
+boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+flags_addr=268435504
+gic_cpu_addr=520093952
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-midr_regval=890236928
+memories=system.nvmem system.physmem
+midr_regval=890224640
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
type=Bridge
delay=50000
filter_ranges_a=0:18446744073709551615
-filter_ranges_b=0:134217727
+filter_ranges_b=0:268435455
nack_delay=4000
req_size_a=16
req_size_b=16
side_a=system.iobus.port[0]
side_b=system.membus.port[0]
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img
+read_only=true
+
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts itb tracer
[system.cpu.tracer]
type=ExeTracer
-[system.diskmem]
-type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
-latency=30000
-latency_var=0
-null=false
-range=134217728:268435455
-zero=false
-port=system.membus.port[1]
-
[system.intrctrl]
type=IntrControl
sys=system
[system.iocache]
type=BaseCache
-addr_range=0:134217727
+addr_range=0:268435455
assoc=8
block_size=64
forward_snoops=false
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.l2c]
type=BaseCache
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[7]
+mem_side=system.membus.port[8]
[system.membus]
type=Bus
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
warn_access=warn
pio=system.membus.default
+[system.nvmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2214592511
+zero=true
+port=system.membus.port[1]
+
[system.physmem]
type=PhysicalMemory
file=
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
+pci_cfg_base=0
system=system
[system.realview.a9scu]
VendorID=32902
config_latency=20000
ctrl_offset=2
-disks=
+disks=system.cf0
io_shift=1
max_backoff_delay=10000000
min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
+pci_bus=2
+pci_dev=7
pci_func=0
pio_latency=1000
platform=system.realview
[system.realview.flash_fake]
type=IsaFake
+fake_mem=true
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
[system.realview.l2x0_fake]
type=IsaFake
+fake_mem=false
pio_addr=520101888
pio_latency=1000
pio_size=4095
warn_access=
pio=system.membus.port[4]
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
-proc_id=201326592
+proc_id0=201326592
+proc_id1=201327138
system=system
pio=system.iobus.port[2]
warn: Sockets disabled, not accepting vnc client connections
-For more information see: http://www.m5sim.org/warn/af6a84f6
warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: The clidr register always reports 0 caches.
-For more information see: http://www.m5sim.org/warn/23a3c326
+warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
-For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
-For more information see: http://www.m5sim.org/warn/2c4acb9c
+warn: instruction 'mcr bpiallis' unimplemented
+warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr icimvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-For more information see: http://www.m5sim.org/warn/7998f2ea
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
+warn: instruction 'mcr icialluis' unimplemented
+warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 2 2011 15:06:32
-M5 started May 2 2011 15:06:36
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
+gem5 compiled Aug 18 2011 16:54:46
+gem5 started Aug 18 2011 17:16:56
+gem5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 114316622000 because m5_exit instruction encountered
+Exiting @ tick 2591441692000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 1455036 # Simulator instruction rate (inst/s)
-host_mem_usage 382532 # Number of bytes of host memory used
-host_seconds 35.16 # Real time elapsed on the host
-host_tick_rate 3251070052 # Simulator tick rate (ticks/s)
+sim_seconds 2.591442 # Number of seconds simulated
+sim_ticks 2591441692000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51162775 # Number of instructions simulated
-sim_seconds 0.114317 # Number of seconds simulated
-sim_ticks 114316622000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11594.610314 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 95143 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 95143 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 75279000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051425 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5158 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5158 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 59805000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051425 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 7815759 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7815759 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.214184 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12650.891296 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7577286 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7577286 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3732392000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.030512 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 238473 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 238473 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3016896000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030512 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 238473 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38196735000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6667481 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6667481 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.618008 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.411843 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 6495289 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6495289 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 7012970000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.025826 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 172192 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 172192 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 6496358500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025826 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 172192 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 931126000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.469586 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu.dcache.demand_accesses::0 14483240 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14483240 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 26165.760413 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 14072575 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14072575 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10745362000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028354 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 410665 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 410665 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9513254500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.028354 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 410665 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 509.189203 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.994510 # Average percentage of cache occupancy
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-system.cpu.dcache.overall_accesses::total 14483240 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 26165.760413 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 14072575 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 14072575 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10745362000 # number of overall miss cycles
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-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 410665 # number of overall misses
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-system.cpu.dcache.overall_mshr_miss_latency 9513254500 # number of overall MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 410665 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 39127861000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 413472 # number of replacements
-system.cpu.dcache.sampled_refs 413984 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 509.189203 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14269857 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 382812 # number of writebacks
-system.cpu.dtb.accesses 15512082 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 2208 # Number of entries that have been flushed from TLB
+host_inst_rate 610490 # Simulator instruction rate (inst/s)
+host_tick_rate 20960550015 # Simulator tick rate (ticks/s)
+host_mem_usage 417836 # Number of bytes of host memory used
+host_seconds 123.63 # Real time elapsed on the host
+sim_insts 75477515 # Number of instructions simulated
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+system.l2c.tagsinuse 24928.376904 # Cycle average of tags in use
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+system.l2c.Writeback_hits::total 610049 # number of Writeback hits
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+system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
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+system.l2c.overall_hits::total 1317328 # number of overall hits
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+system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses
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+system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
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+system.l2c.overall_misses::total 172650 # number of overall misses
+system.l2c.ReadReq_miss_latency 1654516000 # number of ReadReq miss cycles
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+system.l2c.ReadReq_accesses::0 1230045 # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses)
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+system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses)
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+system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses
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+system.l2c.ReadReq_miss_rate::1 0.002952 # miss rate for ReadReq accesses
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+system.l2c.overall_miss_rate::1 0.002952 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.119784 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 52217.642418 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 361.739130 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0 52096.438275 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 243041148.648649 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 52096.438275 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks 103410 # number of writebacks
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+system.l2c.ReadReq_mshr_misses 31722 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 2875 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 140928 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 172650 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 172650 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency 1273844000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 115156000 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5646870000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 6920714000 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 6920714000 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 0.569634 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0 0.116857 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.116857 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 14970647 # DTB read hits
+system.cpu.dtb.read_misses 7343 # DTB read misses
+system.cpu.dtb.write_hits 11215605 # DTB write hits
+system.cpu.dtb.write_misses 2208 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15506431 # DTB hits
+system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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+system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 14977990 # DTB read accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5651 # DTB misses
-system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8731607 # DTB read accesses
-system.cpu.dtb.read_hits 8726923 # DTB read hits
-system.cpu.dtb.read_misses 4684 # DTB read misses
-system.cpu.dtb.write_accesses 6780475 # DTB write accesses
-system.cpu.dtb.write_hits 6779508 # DTB write hits
-system.cpu.dtb.write_misses 967 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 41483736 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.ReadReq_avg_miss_latency::0 14791.732049 # average ReadReq miss latency
+system.cpu.dtb.hits 26186252 # DTB hits
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+system.cpu.dtb.accesses 26195803 # DTB accesses
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+system.cpu.itb.accesses 60362193 # DTB accesses
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+system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
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+system.cpu.icache.overall_hits::total 59504239 # number of overall hits
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system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11790.415195 # average ReadReq mshr miss latency
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-system.cpu.icache.ReadReq_hits::total 41049747 # number of ReadReq hits
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-system.cpu.icache.ReadReq_miss_rate::0 0.010462 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_misses::total 433989 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 5116910500 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 94.587068 # Average number of references to valid blocks.
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+system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14701.087192 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.demand_accesses::total 41483736 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14791.732049 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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-system.cpu.icache.demand_hits::total 41049747 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6419449000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.010462 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 433989 # number of demand (read+write) misses
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-system.cpu.icache.demand_misses::total 433989 # number of demand (read+write) misses
+system.cpu.icache.writebacks 45661 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 5116910500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.010462 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 9984295500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency 350913000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 433989 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 484.311851 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.945922 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0 41483736 # number of overall (read+write) accesses
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-system.cpu.icache.overall_accesses::total 41483736 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14791.732049 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 41049747 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 41049747 # number of overall hits
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-system.cpu.icache.overall_miss_rate::0 0.010462 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 433989 # number of overall misses
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-system.cpu.icache.overall_misses::total 433989 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 5116910500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0.010462 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 433989 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 433477 # number of replacements
-system.cpu.icache.sampled_refs 433989 # Sample count of references to valid blocks.
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+system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 484.311851 # Cycle average of tags in use
-system.cpu.icache.total_refs 41049747 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 34328 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41486666 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41483736 # DTB hits
-system.cpu.itb.inst_accesses 41486666 # ITB inst accesses
-system.cpu.itb.inst_hits 41483736 # ITB inst hits
-system.cpu.itb.inst_misses 2930 # ITB inst misses
-system.cpu.itb.misses 2930 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 228633244 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 228633244 # Number of busy cycles
-system.cpu.num_conditional_control_insts 7015568 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
-system.cpu.num_fp_insts 6058 # number of float instructions
-system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
-system.cpu.num_func_calls 1109778 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
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-system.cpu.num_int_alu_accesses 42435662 # Number of integer alu accesses
-system.cpu.num_int_insts 42435662 # number of integer instructions
-system.cpu.num_int_register_reads 248572490 # number of times the integer registers were read
-system.cpu.num_int_register_writes 49713526 # number of times the integer registers were written
-system.cpu.num_load_insts 9182978 # Number of load instructions
-system.cpu.num_mem_refs 16261071 # number of memory refs
-system.cpu.num_store_insts 7078093 # Number of store instructions
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-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu.dcache.replacements 626903 # number of replacements
+system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use
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+system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 511.875592 # Average occupied blocks per context
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+system.cpu.dcache.WriteReq_hits::0 9958094 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0 247592 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0 23128461 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 23128461 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0 250302 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0 11451 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::0 618865 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0 618865 # number of overall misses
+system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::total 618865 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 5846897000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 9551170500 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 186076500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency 15398067500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 15398067500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0 13538930 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 564388 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.replacements 0 # number of replacements
+system.iocache.tagsinuse 0 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 0 # number of overall misses
+system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks 0 # number of writebacks
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 0 # number of replacements
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 170353 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 170353 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 62556 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 62556 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.632786 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.632786 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 675448 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 6192 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 681640 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 657448 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 6170 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 663618 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.026649 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.003553 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.030202 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 22 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.026682 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 2.910530 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 2.937211 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 29204423000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 72880000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.990756 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 743252000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 417140 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 417140 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 417140 # number of Writeback hits
-system.l2c.Writeback_hits::total 417140 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 7.067586 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 845801 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 6192 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 851993 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.l2c.demand_hits::0 720004 # number of demand (read+write) hits
-system.l2c.demand_hits::1 6170 # number of demand (read+write) hits
-system.l2c.demand_hits::total 726174 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.148731 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.003553 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.152284 # miss rate for demand accesses
-system.l2c.demand_misses::0 125797 # number of demand (read+write) misses
-system.l2c.demand_misses::1 22 # number of demand (read+write) misses
-system.l2c.demand_misses::total 125819 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.148757 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 20.319606 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 20.468363 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 5338.058091 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31318.757980 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.081452 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.477886 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 845801 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 6192 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 851993 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 720004 # number of overall hits
-system.l2c.overall_hits::1 6170 # number of overall hits
-system.l2c.overall_hits::total 726174 # number of overall hits
-system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.148731 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.003553 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.152284 # miss rate for overall accesses
-system.l2c.overall_misses::0 125797 # number of overall misses
-system.l2c.overall_misses::1 22 # number of overall misses
-system.l2c.overall_misses::total 125819 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.148757 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 20.319606 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 20.468363 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 29947675000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 93111 # number of replacements
-system.l2c.sampled_refs 124568 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36656.816071 # Cycle average of tags in use
-system.l2c.total_refs 880395 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 87350 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
-build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
projects / gem5.git / commitdiff