r600g: get rid of r600_texture::array_mode

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 1a78b9762119d557e2686efdcbdf10227f3d6edf..4bb9bf5e09ee28a72accb3c112638827eb32d84b 100644 (file)
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -485,7 +485,7 @@ static bool can_fast_clear_color(struct pipe_context *ctx)
                }
 
                /* only supported on tiled surfaces */
-               if (tex->array_mode[0] < V_028C70_ARRAY_1D_TILED_THIN1) {
+               if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
                    return false;
                }
 

diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 9896470255f47cdc61afb7184761ebbe271e892e..3c0e74ab5de94bdd10d24746b97119a9515cf7fa 100644 (file)
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -37,7 +37,6 @@ struct r600_resource_global {
 struct r600_texture {
        struct r600_resource            resource;
 
-       unsigned                        array_mode[PIPE_MAX_TEXTURE_LEVELS];
        unsigned                        pitch_override;
        unsigned                        size;
        bool                            non_disp_tiling;
@@ -60,8 +59,6 @@ struct r600_texture {
        unsigned                        color_clear_value[2];
 };
 
-#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
-
 struct r600_surface {
        struct pipe_surface             base;
 

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index b74718045ecaea0238a69004db0e5c8b1fae19d8..797506006f0ffda06d03f5f52a19fe5d1877a10d 100644 (file)
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -224,9 +224,7 @@ static int r600_setup_surface(struct pipe_screen *screen,
                              struct r600_texture *rtex,
                              unsigned pitch_in_bytes_override)
 {
-       struct pipe_resource *ptex = &rtex->resource.b.b;
        struct r600_screen *rscreen = (struct r600_screen*)screen;
-       unsigned i;
        int r;
 
        r = rscreen->b.ws->surface_init(rscreen->b.ws, &rtex->surface);
@@ -246,23 +244,6 @@ static int r600_setup_surface(struct pipe_screen *screen,
                        rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
                }
        }
-       for (i = 0; i <= ptex->last_level; i++) {
-               switch (rtex->surface.level[i].mode) {
-               case RADEON_SURF_MODE_LINEAR_ALIGNED:
-                       rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
-                       break;
-               case RADEON_SURF_MODE_1D:
-                       rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
-                       break;
-               case RADEON_SURF_MODE_2D:
-                       rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
-                       break;
-               default:
-               case RADEON_SURF_MODE_LINEAR:
-                       rtex->array_mode[i] = 0;
-                       break;
-               }
-       }
        return 0;
 }
 
@@ -540,7 +521,8 @@ r600_texture_create_object(struct pipe_screen *screen,
        /* Now create the backing buffer. */
        if (!buf) {
                unsigned base_align = rtex->surface.bo_alignment;
-               unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
+               unsigned usage = rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D ?
+                                        PIPE_USAGE_STATIC : base->usage;
 
                if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
                        FREE(rtex);
@@ -847,7 +829,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
         * the CPU is much happier reading out of cached system memory
         * than uncached VRAM.
         */
-       if (R600_TEX_IS_TILED(rtex, level)) {
+       if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D) {
                use_staging_texture = TRUE;
        }