Some cleanups in "ignore specify parser"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index dab5b5919862410dd117bf9083bf415c6898a6e6..0fec445fa4780d53ff46ddda1b7b1ad932641372 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1021,13 +1021,8 @@ list_of_specparam_assignments:
 specparam_assignment:
        ignspec_id '=' constant_mintypmax_expression ;
 
-/*
-pulsestyle_declaration :
-       ;
-
-showcancelled_declaration :
-       ;
-*/
+ignspec_opt_cond:
+       TOK_IF '(' ignspec_expr ')' | /* empty */;
 
 path_declaration :
        simple_path_declaration ';'
@@ -1036,8 +1031,8 @@ path_declaration :
        ;
 
 simple_path_declaration :
-       parallel_path_description '=' path_delay_value |
-       full_path_description '=' path_delay_value
+       ignspec_opt_cond parallel_path_description '=' path_delay_value |
+       ignspec_opt_cond full_path_description '=' path_delay_value
        ;
 
 path_delay_value :
@@ -1047,26 +1042,7 @@ path_delay_value :
        ;
 
 list_of_path_delay_extra_expressions :
-/*
-       t_path_delay_expression
-       | trise_path_delay_expression ',' tfall_path_delay_expression
-       | trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression
-       | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-         tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
-       | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-         tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
-         t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
-         tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
-*/
-       ',' path_delay_expression
-       |  ',' path_delay_expression ',' path_delay_expression
-       |  ',' path_delay_expression ',' path_delay_expression ','
-         path_delay_expression ',' path_delay_expression ',' path_delay_expression
-       |  ',' path_delay_expression ',' path_delay_expression ','
-         path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-         path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-         path_delay_expression ',' path_delay_expression ',' path_delay_expression
-       ;
+       ',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
 
 specify_edge_identifier :
        TOK_POSEDGE | TOK_NEGEDGE ;
@@ -1119,56 +1095,6 @@ system_timing_args :
        system_timing_arg |
        system_timing_args ',' system_timing_arg ;
 
-/*
-t_path_delay_expression :
-       path_delay_expression;
-
-trise_path_delay_expression :
-       path_delay_expression;
-
-tfall_path_delay_expression :
-       path_delay_expression;
-
-tz_path_delay_expression :
-       path_delay_expression;
-
-t01_path_delay_expression :
-       path_delay_expression;
-
-t10_path_delay_expression :
-       path_delay_expression;
-
-t0z_path_delay_expression :
-       path_delay_expression;
-
-tz1_path_delay_expression :
-       path_delay_expression;
-
-t1z_path_delay_expression :
-       path_delay_expression;
-
-tz0_path_delay_expression :
-       path_delay_expression;
-
-t0x_path_delay_expression :
-       path_delay_expression;
-
-tx1_path_delay_expression :
-       path_delay_expression;
-
-t1x_path_delay_expression :
-       path_delay_expression;
-
-tx0_path_delay_expression :
-       path_delay_expression;
-
-txz_path_delay_expression :
-       path_delay_expression;
-
-tzx_path_delay_expression :
-       path_delay_expression;
-*/
-
 path_delay_expression :
        ignspec_constant_expression;
 

diff --git a/tests/various/specify.v b/tests/various/specify.v
index 985879f85184773d40348cef935ab4605da9a1eb..73a59eb7abc1457e73ddcfed7404104d9e76601b 100644 (file)
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,7 +7,7 @@ module test (
                if (EN) Q <= D;
 
        specify
-               if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+               if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
                $setup(D, posedge CLK &&& EN, 5);
                $hold(posedge CLK, D &&& EN, 6);
        endspecify