i965: get num_images from shader_info rather than gl_linked_shader

This is a step towards freeing gl_linked_shader after linking.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index e67b957a267112ef65693510546943961fa42db2..0c4783288d82adc2004cc03293a663442bade99c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -278,8 +278,8 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
          ctx->_Shader->CurrentProgram[i] ?
             ctx->_Shader->CurrentProgram[i]->_LinkedShaders[i] : NULL;
 
-      if (unlikely(shader && shader->NumImages)) {
-         for (unsigned j = 0; j < shader->NumImages; j++) {
+      if (unlikely(shader && shader->Program->info.num_images)) {
+         for (unsigned j = 0; j < shader->Program->info.num_images; j++) {
             struct gl_image_unit *u = &ctx->ImageUnits[shader->ImageUnits[j]];
             tex_obj = intel_texture_object(u->TexObj);
 

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 3790b6d2c6a4b1b21e086fb764c2e23160292fc1..799ae75742d27c42c88685f77e04a2055ecb4c54 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1515,6 +1515,7 @@ void brw_upload_abo_surfaces(struct brw_context *brw,
                              struct brw_stage_prog_data *prog_data);
 void brw_upload_image_surfaces(struct brw_context *brw,
                                struct gl_linked_shader *shader,
+                               const struct gl_program *prog,
                                struct brw_stage_state *stage_state,
                                struct brw_stage_prog_data *prog_data);
 

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index 8b13b49b6ff2b94135e58821fcb29d34eab4a717..ab445ab2fdffaffc20b64249631d79482e3d423d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -103,9 +103,10 @@ brw_codegen_cs_prog(struct brw_context *brw,
    prog_data.base.pull_param =
       rzalloc_array(NULL, const gl_constant_value *, param_count);
    prog_data.base.image_param =
-      rzalloc_array(NULL, struct brw_image_param, cs->base.NumImages);
+      rzalloc_array(NULL, struct brw_image_param,
+                    cp->program.info.num_images);
    prog_data.base.nr_params = param_count;
-   prog_data.base.nr_image_params = cs->base.NumImages;
+   prog_data.base.nr_image_params = cp->program.info.num_images;
 
    brw_nir_setup_glsl_uniforms(cp->program.nir, prog, &cp->program,
                                &prog_data.base, true);

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 77efa6382c51946547de9f6e3538291de4b626fd..6bdedb96574007b9120bc3e4ec3bb1a3683631d4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -125,9 +125,10 @@ brw_codegen_gs_prog(struct brw_context *brw,
    prog_data.base.base.pull_param =
       rzalloc_array(NULL, const gl_constant_value *, param_count);
    prog_data.base.base.image_param =
-      rzalloc_array(NULL, struct brw_image_param, gs->NumImages);
+      rzalloc_array(NULL, struct brw_image_param,
+                    gp->program.info.num_images);
    prog_data.base.base.nr_params = param_count;
-   prog_data.base.base.nr_image_params = gs->NumImages;
+   prog_data.base.base.nr_image_params = gp->program.info.num_images;
 
    brw_nir_setup_glsl_uniforms(gp->program.nir, prog, &gp->program,
                                &prog_data.base.base,

diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
index 4d0f50c9c11d73c0a6a7755882c77ef26ec55ae8..dd43edfec85b19bff41e661d96e92645a96c4abb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
@@ -129,11 +129,12 @@ brw_upload_gs_image_surfaces(struct brw_context *brw)
    /* BRW_NEW_GEOMETRY_PROGRAM */
    struct gl_shader_program *prog =
       ctx->_Shader->CurrentProgram[MESA_SHADER_GEOMETRY];
+   const struct gl_program *gp = brw->geometry_program;
 
-   if (prog) {
+   if (gp && prog) {
       /* BRW_NEW_GS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
       brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
-                                &brw->gs.base, brw->gs.base.prog_data);
+                                gp, &brw->gs.base, brw->gs.base.prog_data);
    }
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 61bc868db9e0f84558bf40a4651488fb958b6013..db797184db526ea82f03c4c67e7b3aeb08709896 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1231,9 +1231,9 @@ brw_assign_common_binding_table_offsets(gl_shader_stage stage,
       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
    }
 
-   if (shader && shader->NumImages) {
+   if (prog->info.num_images) {
       stage_prog_data->binding_table.image_start = next_binding_table_offset;
-      next_binding_table_offset += shader->NumImages;
+      next_binding_table_offset += prog->info.num_images;
    } else {
       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
    }

diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index 24cc423e60c55f23745d6585fd3f453b4c063603..87a956faf5093ec3bd78dbfc8c0961bb05f8f898 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -201,8 +201,6 @@ brw_codegen_tcs_prog(struct brw_context *brw,
     * padding around uniform values below vec4 size, so the worst case is that
     * every uniform is a float which gets padded to the size of a vec4.
     */
-   struct gl_linked_shader *tcs = shader_prog ?
-      shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] : NULL;
    int param_count = nir->num_uniforms / 4;
 
    prog_data.base.base.param =
@@ -211,14 +209,15 @@ brw_codegen_tcs_prog(struct brw_context *brw,
       rzalloc_array(NULL, const gl_constant_value *, param_count);
    prog_data.base.base.nr_params = param_count;
 
-   if (tcs) {
+   if (tcp) {
       brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL, devinfo,
                                               shader_prog, &tcp->program,
                                               &prog_data.base.base, 0);
 
       prog_data.base.base.image_param =
-         rzalloc_array(NULL, struct brw_image_param, tcs->NumImages);
-      prog_data.base.base.nr_image_params = tcs->NumImages;
+         rzalloc_array(NULL, struct brw_image_param,
+                       tcp->program.info.num_images);
+      prog_data.base.base.nr_image_params = tcp->program.info.num_images;
 
       brw_nir_setup_glsl_uniforms(nir, shader_prog, &tcp->program,
                                   &prog_data.base.base,
@@ -278,6 +277,8 @@ brw_codegen_tcs_prog(struct brw_context *brw,
    }
 
    if (unlikely(brw->perf_debug)) {
+      struct gl_linked_shader *tcs = shader_prog ?
+         shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] : NULL;
       struct brw_shader *btcs = (struct brw_shader *) tcs;
       if (btcs) {
          if (btcs->compiled_once) {

diff --git a/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
index 83b561190bb34b4fdad9dca28dee49b1b94cc26c..06bdfa3762f626156bbdee107216996668f7bf2d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
@@ -129,11 +129,12 @@ brw_upload_tcs_image_surfaces(struct brw_context *brw)
    /* BRW_NEW_TESS_PROGRAMS */
    struct gl_shader_program *prog =
       ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_CTRL];
+   const struct gl_program *tcp = brw->tess_ctrl_program;
 
-   if (prog) {
+   if (tcp && prog) {
       /* BRW_NEW_TCS_PROG_DATA, BRW_NEW_IMAGE_UNITS */
       brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_CTRL],
-                                &brw->tcs.base, brw->tcs.base.prog_data);
+                                tcp, &brw->tcs.base, brw->tcs.base.prog_data);
    }
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index 160f21e597f22dca3731a1a3bc3866f2863799a1..b2d41c15557ba128b754efd08f09426426f61c98 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -150,8 +150,6 @@ brw_codegen_tes_prog(struct brw_context *brw,
     * padding around uniform values below vec4 size, so the worst case is that
     * every uniform is a float which gets padded to the size of a vec4.
     */
-   struct gl_linked_shader *tes =
-      shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
    int param_count = nir->num_uniforms / 4;
 
    prog_data.base.base.param =
@@ -159,9 +157,10 @@ brw_codegen_tes_prog(struct brw_context *brw,
    prog_data.base.base.pull_param =
       rzalloc_array(NULL, const gl_constant_value *, param_count);
    prog_data.base.base.image_param =
-      rzalloc_array(NULL, struct brw_image_param, tes->NumImages);
+      rzalloc_array(NULL, struct brw_image_param,
+                    tep->program.info.num_images);
    prog_data.base.base.nr_params = param_count;
-   prog_data.base.base.nr_image_params = tes->NumImages;
+   prog_data.base.base.nr_image_params = tep->program.info.num_images;
 
    prog_data.base.cull_distance_mask =
       ((1 << tep->program.CullDistanceArraySize) - 1) <<
@@ -200,6 +199,8 @@ brw_codegen_tes_prog(struct brw_context *brw,
    }
 
    if (unlikely(brw->perf_debug)) {
+      struct gl_linked_shader *tes =
+         shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
       struct brw_shader *btes = (struct brw_shader *) tes;
       if (btes->compiled_once) {
          brw_tes_debug_recompile(brw, shader_prog, key);

diff --git a/src/mesa/drivers/dri/i965/brw_tes_surface_state.c b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
index 53b39cd29e76ce740a6192b46217d14d82dc2eb5..1b31b203a1120e4b3439fcf0107a1ea2ef74e79f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
@@ -129,11 +129,12 @@ brw_upload_tes_image_surfaces(struct brw_context *brw)
    /* BRW_NEW_TESS_PROGRAMS */
    struct gl_shader_program *prog =
       ctx->_Shader->CurrentProgram[MESA_SHADER_TESS_EVAL];
+   const struct gl_program *tep = brw->tess_eval_program;
 
-   if (prog) {
+   if (tep && prog) {
       /* BRW_NEW_TES_PROG_DATA, BRW_NEW_IMAGE_UNITS */
       brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_TESS_EVAL],
-                                &brw->tes.base, brw->tes.base.prog_data);
+                                tep, &brw->tes.base, brw->tes.base.prog_data);
    }
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index edb577f570a28129c505dd0972193ad5cb4df1b6..86cd1bf8bcae8ac5cd5aedecedf22b29ae96dce9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -122,8 +122,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
     */
    int param_count = vp->program.nir->num_uniforms / 4;
 
-   if (vs)
-      prog_data.base.base.nr_image_params = vs->base.NumImages;
+   prog_data.base.base.nr_image_params = vp->program.info.num_images;
 
    /* vec4_visitor::setup_uniform_clipplane_values() also uploads user clip
     * planes as uniforms.

diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 6a97cd4a13f7d240a21f49eced80d225fce5ab92..891fd5db3f221423d476f54ae8903e3223ba1063 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -195,11 +195,12 @@ brw_upload_vs_image_surfaces(struct brw_context *brw)
    /* BRW_NEW_VERTEX_PROGRAM */
    struct gl_shader_program *prog =
       ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX];
+   const struct gl_program *vp = brw->vertex_program;
 
-   if (prog) {
+   if (vp && prog) {
       /* BRW_NEW_VS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
       brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX],
-                                &brw->vs.base, brw->vs.base.prog_data);
+                                vp, &brw->vs.base, brw->vs.base.prog_data);
    }
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 14ecaa858716cadfd6fcaf5440a0774d98d1c05b..e6f68c46f8b9a94ae3b5fac1e27345fc31a95a9b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -107,8 +107,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
     * by the state cache.
     */
    int param_count = fp->program.nir->num_uniforms / 4;
-   if (fs)
-      prog_data.base.nr_image_params = fs->base.NumImages;
+   prog_data.base.nr_image_params = fp->program.info.num_images;
    /* The backend also sometimes adds params for texture size. */
    param_count += 2 * ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits;
    prog_data.base.param =

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 835a46867491d77dacdab53a9967abf639eb7ebf..c275b71ed4b6d45df0fb24f942d6e67a37a09083 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1568,11 +1568,12 @@ brw_upload_cs_image_surfaces(struct brw_context *brw)
    /* _NEW_PROGRAM */
    struct gl_shader_program *prog =
       ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+   const struct gl_program *cp = brw->compute_program;
 
-   if (prog) {
+   if (cp && prog) {
       /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
       brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
-                                &brw->cs.base, brw->cs.base.prog_data);
+                                cp, &brw->cs.base, brw->cs.base.prog_data);
    }
 }
 
@@ -1779,13 +1780,15 @@ update_image_surface(struct brw_context *brw,
 void
 brw_upload_image_surfaces(struct brw_context *brw,
                           struct gl_linked_shader *shader,
+                          const struct gl_program *prog,
                           struct brw_stage_state *stage_state,
                           struct brw_stage_prog_data *prog_data)
 {
+   assert(prog);
    struct gl_context *ctx = &brw->ctx;
 
-   if (shader && shader->NumImages) {
-      for (unsigned i = 0; i < shader->NumImages; i++) {
+   if (prog->info.num_images && shader) {
+      for (unsigned i = 0; i < prog->info.num_images; i++) {
          struct gl_image_unit *u = &ctx->ImageUnits[shader->ImageUnits[i]];
          const unsigned surf_idx = prog_data->binding_table.image_start + i;
 
@@ -1810,11 +1813,12 @@ brw_upload_wm_image_surfaces(struct brw_context *brw)
    struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_FRAGMENT_PROGRAM */
    struct gl_shader_program *prog = ctx->_Shader->_CurrentFragmentProgram;
+   const struct gl_program *wm = brw->fragment_program;
 
-   if (prog) {
+   if (wm && prog) {
       /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
       brw_upload_image_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
-                                &brw->wm.base, brw->wm.base.prog_data);
+                                wm, &brw->wm.base, brw->wm.base.prog_data);
    }
 }