Fixed simlib entries for $memrd and $memwr

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e241cd3cee4c3eb4d6b0f7c2e0d075b785660ed7..bacf4a17ef96a2f672905d9a92ed3eeeb3616b56 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1449,6 +1449,7 @@ parameter WIDTH = 8;
 
 parameter CLK_ENABLE = 0;
 parameter CLK_POLARITY = 0;
+parameter TRANSPARENT = 0;
 
 input CLK;
 input [ABITS-1:0] ADDR;
@@ -1473,6 +1474,7 @@ parameter WIDTH = 8;
 
 parameter CLK_ENABLE = 0;
 parameter CLK_POLARITY = 0;
+parameter PRIORITY = 0;
 
 input CLK;
 input [WIDTH-1:0] EN;