(no commit message)

diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn
index c5bd20a12bf0ab6322d224319f9af301bcf74b65..7c0eaef0eda7d0e61b51cfd866ad3975993cbc82 100644 (file)
--- a/openpower/sv/predication.mdwn
+++ b/openpower/sv/predication.mdwn
@@ -43,7 +43,7 @@ Adding a full set special vector opcodes just for manipulating predicate masks a
 
 this involves treating each CR as providing one bit of predicate. If
 there is limited space in SVPrefix it will be a fixed bit (bit 0)
-otherwise it may be selected (bit 0 to 3 of the CR)
+otherwise it may be selected (bit 0 to 3 of the CR) through a firld in the opcode.
 
 the crucial advantage of this proposal is that the Function Units can
 have one more register (a CR) added as their Read Dependency Hazards