sdram: pass module as phy parameter, define memtype in modules and only keep phy...

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 8c165189677ebaa95357f516389ccb0c8a1face5..ccdc9fcb30c26f95cb1db5ac03a4f46710144b93 100644 (file)
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -21,8 +21,9 @@ from migen.fhdl.std import *
 from misoclib.mem import sdram
 
 class SDRAMModule:
-       def __init__(self, clk_freq, geom_settings, timing_settings):
+       def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
                self.clk_freq = clk_freq
+               self.memtype = memtype
                self.geom_settings = sdram.GeomSettings(
                        databits=geom_settings["nbits"],
                        bankbits=log2_int(geom_settings["nbanks"]),
@@ -62,7 +63,7 @@ class IS42S16160(SDRAMModule):
                "tRFC":         70
        }
        def __init__(self, clk_freq):
-               SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+               SDRAMModule.__init__(self, clk_freq,  "SDR", self.geom_settings,
                        self.timing_settings)
 
 class MT48LC4M16(SDRAMModule):
@@ -81,7 +82,7 @@ class MT48LC4M16(SDRAMModule):
                "tRFC":         66
        }
        def __init__(self, clk_freq):
-               SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+               SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
                        self.timing_settings)
 
 class AS4C16M16(SDRAMModule):
@@ -101,7 +102,7 @@ class AS4C16M16(SDRAMModule):
                "tRFC":         60
        }
        def __init__(self, clk_freq):
-               SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+               SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
                        self.timing_settings)
 
 # DDR
@@ -121,7 +122,7 @@ class MT46V32M16(SDRAMModule):
                "tRFC":         70
        }
        def __init__(self, clk_freq):
-               SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+               SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
                        self.timing_settings)
 
 # LPDDR
@@ -141,7 +142,7 @@ class MT46H32M16(SDRAMModule):
                "tRFC":         72
        }
        def __init__(self, clk_freq):
-               SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+               SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
                        self.timing_settings)
 
 # DDR2
@@ -161,7 +162,7 @@ class MT47H128M8(SDRAMModule):
                "tRFC":         127.5
        }
        def __init__(self, clk_freq):
-               SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+               SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
                        self.timing_settings)
 
 # DDR3
@@ -181,5 +182,5 @@ class MT8JTF12864(SDRAMModule):
                "tRFC":         70
        }
        def __init__(self, clk_freq):
-               SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+               SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
                        self.timing_settings)

diff --git a/misoclib/mem/sdram/phy/gensdrphy.py b/misoclib/mem/sdram/phy/gensdrphy.py
index 4ed27060d973fe47839d945262675c404e145355..12a4f30c17cf8bf89d0b354dc6f30667d56a91ee 100644 (file)
--- a/misoclib/mem/sdram/phy/gensdrphy.py
+++ b/misoclib/mem/sdram/phy/gensdrphy.py
@@ -29,13 +29,13 @@ from misoclib.mem.sdram.phy.dfi import *
 from misoclib.mem import sdram
 
 class GENSDRPHY(Module):
-       def __init__(self, pads):
+       def __init__(self, pads, module):
                addressbits = flen(pads.a)
                bankbits = flen(pads.ba)
                databits = flen(pads.dq)
 
                self.settings = sdram.PhySettings(
-                       memtype="SDR",
+                       memtype=module.memtype,
                        dfi_databits=databits,
                        nphases=1,
                        rdphase=0,
@@ -46,6 +46,7 @@ class GENSDRPHY(Module):
                        read_latency=4,
                        write_latency=0
                )
+               self.module = module
 
                self.dfi = Interface(addressbits, bankbits, databits)
 

diff --git a/misoclib/mem/sdram/phy/k7ddrphy.py b/misoclib/mem/sdram/phy/k7ddrphy.py
index 5e0c22a38c7907a9e9a7fd1f41e192c7bdbaac24..984bdea2ada5bf0c327d4294d7d1120271369569 100644 (file)
--- a/misoclib/mem/sdram/phy/k7ddrphy.py
+++ b/misoclib/mem/sdram/phy/k7ddrphy.py
@@ -7,7 +7,7 @@ from misoclib.mem.sdram.phy.dfi import *
 from misoclib.mem import sdram
 
 class K7DDRPHY(Module, AutoCSR):
-       def __init__(self, pads, memtype):
+       def __init__(self, pads, module):
                addressbits = flen(pads.a)
                bankbits = flen(pads.ba)
                databits = flen(pads.dq)
@@ -25,7 +25,7 @@ class K7DDRPHY(Module, AutoCSR):
                self._wdly_dqs_inc = CSR()
 
                self.settings = sdram.PhySettings(
-                       memtype=memtype,
+                       memtype=module.memtype,
                        dfi_databits=2*databits,
                        nphases=nphases,
                        rdphase=0,
@@ -37,6 +37,7 @@ class K7DDRPHY(Module, AutoCSR):
                        read_latency=6,
                        write_latency=2
                )
+               self.module = module
 
                self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
 

diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py
index c7a3433ae3c99363c0f11c5bb9c9c5a9fb1e43aa..1f505df67d3d3d5e5ddd5f94f5b62f9d091864a8 100644 (file)
--- a/misoclib/mem/sdram/phy/s6ddrphy.py
+++ b/misoclib/mem/sdram/phy/s6ddrphy.py
@@ -21,8 +21,8 @@ from misoclib.mem.sdram.phy.dfi import *
 from misoclib.mem import sdram
 
 class S6DDRPHY(Module):
-       def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
-               if memtype not in ["DDR", "LPDDR", "DDR2"]:
+       def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
+               if module.memtype not in ["DDR", "LPDDR", "DDR2"]:
                        raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
                addressbits = flen(pads.a)
                bankbits = flen(pads.ba)
@@ -30,7 +30,7 @@ class S6DDRPHY(Module):
                nphases = 2
 
                self.settings = sdram.PhySettings(
-                       memtype=memtype,
+                       memtype=module.memtype,
                        dfi_databits=2*databits,
                        nphases=nphases,
                        rdphase=0,
@@ -41,6 +41,7 @@ class S6DDRPHY(Module):
                        read_latency=5,
                        write_latency=0
                )
+               self.module = module
 
                self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
                self.clk4x_wr_strb = Signal()

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index b34264e04f3883c2054a65a2c5f5aed63498872e..d18a6799e207c437d1513132ea25fd52db914bfe 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -26,7 +26,7 @@ class SDRAMSoC(SoC):
                        self.sdram_controller_settings = sdram_controller_settings
                self._sdram_phy_registered = False
 
-       def register_sdram_phy(self, phy, geom_settings, timing_settings):
+       def register_sdram_phy(self, phy):
                if self._sdram_phy_registered:
                        raise FinalizeError
                self._sdram_phy_registered = True
@@ -34,7 +34,7 @@ class SDRAMSoC(SoC):
                        raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
 
                # Core
-               self.submodules.sdram = SDRAMCore(phy, geom_settings, timing_settings, self.sdram_controller_settings)
+               self.submodules.sdram = SDRAMCore(phy, phy.module.geom_settings, phy.module.timing_settings, self.sdram_controller_settings)
 
                # LASMICON frontend
                if isinstance(self.sdram_controller_settings, LASMIconSettings):
@@ -63,7 +63,9 @@ class SDRAMSoC(SoC):
                # MINICON frontend
                elif isinstance(self.sdram_controller_settings, MiniconSettings):
                        sdram_width = flen(self.sdram.controller.bus.dat_r)
-                       main_ram_size = 2**(geom_settings.bankbits+geom_settings.rowbits+geom_settings.colbits)*sdram_width//8
+                       main_ram_size = 2**(phy.module.geom_settings.bankbits+
+                                                               phy.module.geom_settings.rowbits+
+                                                               phy.module.geom_settings.colbits)*sdram_width//8
 
                        if sdram_width == 32:
                                self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)

diff --git a/targets/de0nano.py b/targets/de0nano.py
index a1fd027d50b1233b2408369688262b52ffe7bb20..317843c93cbec181a6671ce1a92cb353b8627fbb 100644 (file)
--- a/targets/de0nano.py
+++ b/targets/de0nano.py
@@ -93,8 +93,7 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform)
 
                if not self.with_integrated_main_ram:
-                       sdram_module = IS42S16160(self.clk_freq)
-                       self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-                       self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
+                       self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), IS42S16160(self.clk_freq))
+                       self.register_sdram_phy(self.sdrphy)
 
 default_subtarget = BaseSoC

diff --git a/targets/kc705.py b/targets/kc705.py
index a26bb712c574f91af9b55b0bb7d92701dca60c37..7cecd5089476fb0e42aecd591dc4e2d1e1a671bd 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -86,9 +86,8 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform)
 
                if not self.with_integrated_main_ram:
-                       sdram_modules = MT8JTF12864(self.clk_freq)
-                       self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
-                       self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
+                       self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), MT8JTF12864(self.clk_freq))
+                       self.register_sdram_phy(self.ddrphy)
 
                spiflash_pads = platform.request("spiflash")
                spiflash_pads.clk = Signal()

diff --git a/targets/minispartan6.py b/targets/minispartan6.py
index 04e6d00495880bf53e2b6042b1bfd56d2441ed69..82e9fb783010699be7b64452ebbca9071867e520 100644 (file)
--- a/targets/minispartan6.py
+++ b/targets/minispartan6.py
@@ -73,8 +73,7 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform, clk_freq)
 
                if not self.with_integrated_main_ram:
-                       sdram_module = AS4C16M16(clk_freq)
-                       self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-                       self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
+                       self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), AS4C16M16(clk_freq))
+                       self.register_sdram_phy(self.sdrphy)
 
 default_subtarget = BaseSoC

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index a193e7635de28708e9043622de84a8c272222814..d83d955bb87007787153dfd6f081e1e04b647e1c 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -44,10 +44,9 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
                if not self.with_integrated_main_ram:
-                       sdram_modules = MT46V32M16(self.clk_freq)
-                       self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
+                       self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46V32M16(self.clk_freq),
                                rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
-                       self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
+                       self.register_sdram_phy(self.ddrphy)
 
                        self.comb += [
                                self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 57f1d419993cd2f87d5a13cbc2f4dd3832247bc3..d12a1a2b81b8f2f2af135f4e13bf2eb62d3cf5aa 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -102,9 +102,8 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform, clk_freq)
 
                if not self.with_integrated_main_ram:
-                       sdram_module = MT46H32M16(self.clk_freq)
-                       self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
-                               "LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
+                       self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46H32M16(self.clk_freq),
+                               rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
                        self.comb += [
                                self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
                                self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
@@ -112,7 +111,7 @@ class BaseSoC(SDRAMSoC):
                        platform.add_platform_command("""
        PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
        """)
-                       self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
+                       self.register_sdram_phy(self.ddrphy)
 
                self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
                # If not in ROM, BIOS is in SPI flash

diff --git a/targets/ppro.py b/targets/ppro.py
index 01c332d1a54d77436105552ba346b7bb80f7e116..da27a6e2fa33b731dd4ab55f4a975bd346ba5c8e 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -78,9 +78,8 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform, clk_freq)
 
                if not self.with_integrated_main_ram:
-                       sdram_module = MT48LC4M16(clk_freq)
-                       self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-                       self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
+                       self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), MT48LC4M16(clk_freq))
+                       self.register_sdram_phy(self.sdrphy)
 
                self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
                self.flash_boot_address = 0x70000