(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 07589c2f6136fdbedcce4f405fd4fd77ad1768ea..99b33f7de373e7059563dc68fa0caa0d9db0e9c9 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -571,13 +571,13 @@ alternative which is understandable and, if EXTRA2 is zero will map to
 | 10       | Vector | `r0-r124`/4 | `RA 0b00`      |
 | 11       | Vector | `r2-r126`/4 | `RA 0b10`   |
 
-## CR EXTRA3
+## CR Field EXTRA3
 
-CR encoding is essentially the same but made more complex due to CRs being bit-based.  See [[svp64/appendix]] for explanation and pseudocode.
+CR Field encoding is essentially the same but made more complex due to CRs being bit-based.  See [[svp64/appendix]] for explanation and pseudocode.
 
 Encoding shown MSB down to LSB
 
-5-bit (BA, BB, BT):
+For a 5-bit operand (BA, BB, BT):
 
 | Value | Mode | Range/Inc     | 8..5      | 4..2    | 1..0    |
 |-------|------|---------------|-----------| --------|---------|
@@ -590,7 +590,7 @@ Encoding shown MSB down to LSB
 | 110   | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000   | BA[1:0] |
 | 111   | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100   | BA[1:0] |
 
-3-bit (BFA):
+For a 3-bit operand (e.g. BFA):
 
 | Value | Mode | Range/Inc     | 6..3      | 2..0    |
 |-------|------|---------------|-----------| --------|
@@ -609,6 +609,8 @@ CR encoding is essentially the same but made more complex due to CRs being bit-b
 
 Encoding shown MSB down to LSB
 
+For a 5-bit operand (BA, BB, BC):
+
 | Value | Mode   | Range/Inc      | 8..5    | 4..2    | 1..0    |
 |-------|--------|----------------|---------|---------|---------|
 | 00    | Scalar | `CR0-CR7`/1    | 0b0000  | BA[4:2] | BA[1:0] |
@@ -616,6 +618,15 @@ Encoding shown MSB down to LSB
 | 10    | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000   | BA[1:0] |
 | 11    | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000   | BA[1:0] |
 
+For a 3-bit operand (e.g. BFA):
+
+| Value | Mode | Range/Inc     | 6..3      | 2..0    |
+|-------|------|---------------|-----------| --------|
+| 00    | Scalar | `CR0-CR7`/1   | 0b0000  | BFA   |
+| 01    | Scalar | `CR8-CR15`/1  | 0b0001  | BFA     |
+| 10    | Vector | `CR0-CR112`/16 | BFA 0 | 0b000   |
+| 11    | Vector | `CR8-CR120`/16 | BFA 1 | 0b000   |
+
 # Appendix
 
 Now at its own page: [[svp64/appendix]]