Initial Sapphire Rapids and Alder Lake support from ISA r40

gcc/
	* common/config/i386/cpuinfo.h
	(get_intel_cpu): Handle sapphirerapids.
	* common/config/i386/i386-common.c
	(processor_names): Add sapphirerapids and alderlake.
	(processor_alias_table): Add sapphirerapids and alderlake.
	* common/config/i386/i386-cpuinfo.h
	(processor_subtypes): Add INTEL_COREI7_ALDERLAKE and
	INTEL_COREI7_ALDERLAKE.
	* config.gcc: Add -march=sapphirerapids and alderlake.
	* config/i386/driver-i386.c
	(host_detect_local_cpu) Handle sapphirerapids and alderlake.
	* config/i386/i386-c.c
	(ix86_target_macros_internal): Handle sapphirerapids and alderlake.
	* config/i386/i386-options.c
	(m_SAPPHIRERAPIDS) : Define.
	(m_ALDERLAKE): Ditto.
	(m_CORE_AVX512) : Add m_SAPPHIRERAPIDS.
	(processor_cost_table): Add sapphirerapids and alderlake.
	(ix86_option_override_internal) Handle PTA_WAITPKG, PTA_ENQCMD,
	PTA_CLDEMOTE, PTA_SERIALIZE, PTA_TSXLDTRK.
	* config/i386/i386.h
	(ix86_size_cost) : Define SAPPHIRERAPIDS and ALDERLAKE.
	(processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and
	PROCESSOR_ALDERLAKE.
	(PTA_ENQCMD): New.
	(PTA_CLDEMOTE): Ditto.
	(PTA_SERIALIZE): Ditto.
	(PTA_TSXLDTRK): New.
	(PTA_SAPPHIRERAPIDS): Ditto.
	(PTA_ALDERLAKE): Ditto.
	(processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and
	PROCESSOR_ALDERLAKE.
	* doc/extend.texi: Add sapphirerapids and alderlake.
	* doc/invoke.texi: Add sapphirerapids and alderlake.

gcc/testsuite/
	* gcc.target/i386/funcspec-56.inc: Handle new march.
	* g++.target/i386/mv16.C: Handle new march

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 3eda53240f67e45244f7de65f3dac50ec2305d95..b14c7c668daf8665dfba6f2e1bae71637443d91d 100644 (file)
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -456,6 +456,14 @@ get_intel_cpu (struct __processor_model *cpu_model,
       cpu_model->__cpu_type = INTEL_COREI7;
       cpu_model->__cpu_subtype = INTEL_COREI7_TIGERLAKE;
       break;
+    case 0x8f:
+      /* Sapphire Rapids.  */
+      cpu = "sapphirerapids";
+      CHECK___builtin_cpu_is ("corei7");
+      CHECK___builtin_cpu_is ("sapphirerapids");
+      cpu_model->__cpu_type = INTEL_COREI7;
+      cpu_model->__cpu_subtype = INTEL_COREI7_SAPPHIRERAPIDS;
+      break;
     case 0x17:
     case 0x1d:
       /* Penryn.  */

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 654df68d6885b12d595c9ed479c9a1806d5cdde3..bb14305ad7b7fa6ddcc78b842825cd3a882e9a18 100644 (file)
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1598,6 +1598,8 @@ const char *const processor_names[] =
   "cascadelake",
   "tigerlake",
   "cooperlake",
+  "sapphirerapids",
+  "alderlake",
   "intel",
   "geode",
   "k6",
@@ -1703,6 +1705,10 @@ const pta processor_alias_table[] =
     M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
   {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
     M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
+  {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
+    M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
+  {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
+    M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
   {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
     M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
   {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,

diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 96cf0eaea4733cf875c5f0979e3454146762b150..84ca97e7ade71dc2ec2c1027ce4f9fe1963343d2 100644 (file)
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -84,6 +84,8 @@ enum processor_subtypes
   INTEL_COREI7_CASCADELAKE,
   INTEL_COREI7_TIGERLAKE,
   INTEL_COREI7_COOPERLAKE,
+  INTEL_COREI7_SAPPHIRERAPIDS,
+  INTEL_COREI7_ALDERLAKE,
   CPU_SUBTYPE_MAX
 };
 

diff --git a/gcc/config.gcc b/gcc/config.gcc
index c0460686e21355e17ed823328f07ade9ca532e44..30b51c3dc81e85f9e072b36b860b2d3b17952c53 100644 (file)
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -667,8 +667,8 @@ bdver3 bdver4 znver1 znver2 btver1 btver2 k8 k8-sse3 opteron \
 opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \
 slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
 silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
-skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake x86-64 \
-native"
+skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \
+sapphirerapids alderlake x86-64 native"
 
 # Additional x86 processors supported by --with-cpu=.  Each processor
 # MUST be separated by exactly one space.

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 6da2a15c1b04c3c9b9d959492ef242dd3b3ea14a..ecdad5765d57da70da7f35dcc62bb5fb7addb27b 100644 (file)
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -563,9 +563,15 @@ const char *host_detect_local_cpu (int argc, const char **argv)
              /* This is unknown family 0x6 CPU.  */
              if (has_feature (FEATURE_AVX))
                {
-                 /* Assume Tiger Lake */
                  if (has_feature (FEATURE_AVX512VP2INTERSECT))
-                   cpu = "tigerlake";
+                   {
+                     if (has_feature (FEATURE_TSXLDTRK))
+                       /* Assume Sapphire Rapids.  */
+                       cpu = "sapphirerapids";
+                     else
+                       /* Assume Tiger Lake */
+                       cpu = "tigerlake";
+                   }
                  /* Assume Cooper Lake */
                  else if (has_feature (FEATURE_AVX512BF16))
                    cpu = "cooperlake";
@@ -587,6 +593,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
                /* Assume Skylake with AVX-512.  */
                else if (has_feature (FEATURE_AVX512F))
                  cpu = "skylake-avx512";
+                /* Assume Alder Lake */
+               else if (has_feature (FEATURE_SERIALIZE))
+                   cpu = "alderlake";
                /* Assume Skylake.  */
                else if (has_feature (FEATURE_CLFLUSHOPT))
                  cpu = "skylake";

diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 891b2c68372ef9199c9aebcbf544b7b2c400e35d..2d61a0ce70acd1d7c687d2ae78a328104b20ab74 100644 (file)
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -229,6 +229,15 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_COOPERLAKE:
       def_or_undef (parse_in, "__cooperlake");
       def_or_undef (parse_in, "__cooperlake__");
+      break;
+    case PROCESSOR_SAPPHIRERAPIDS:
+      def_or_undef (parse_in, "__sapphirerapids");
+      def_or_undef (parse_in, "__sapphirerapids__");
+      break;
+    case PROCESSOR_ALDERLAKE:
+      def_or_undef (parse_in, "__alderlake");
+      def_or_undef (parse_in, "__alderlake__");
+      break;
     /* use PROCESSOR_max to not set/unset the arch macro.  */
     case PROCESSOR_max:
       break;
@@ -383,6 +392,12 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_COOPERLAKE:
       def_or_undef (parse_in, "__tune_cooperlake__");
       break;
+    case PROCESSOR_SAPPHIRERAPIDS:
+      def_or_undef (parse_in, "__tune_sapphirerapids__");
+      break;
+    case PROCESSOR_ALDERLAKE:
+      def_or_undef (parse_in, "__tune_alderlake__");
+      break;
     case PROCESSOR_INTEL:
     case PROCESSOR_GENERIC:
       break;

diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index 67480b2deea75e4c1549ddc5b04dd125c0520463..26d1ea18ef1744dd2fd773f5dbbd10551d4b1910 100644 (file)
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -122,9 +122,11 @@ along with GCC; see the file COPYING3.  If not see
 #define m_CASCADELAKE (HOST_WIDE_INT_1U<<PROCESSOR_CASCADELAKE)
 #define m_TIGERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_TIGERLAKE)
 #define m_COOPERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_COOPERLAKE)
+#define m_SAPPHIRERAPIDS (HOST_WIDE_INT_1U<<PROCESSOR_SAPPHIRERAPIDS)
+#define m_ALDERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ALDERLAKE)
 #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
                       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \
-                      | m_TIGERLAKE | m_COOPERLAKE)
+                      | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS)
 #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
 #define m_CORE_ALL (m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2)
 #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
@@ -719,6 +721,8 @@ static const struct processor_costs *processor_cost_table[] =
   &skylake_cost,
   &skylake_cost,
   &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
   &intel_cost,
   &geode_cost,
   &k6_cost,
@@ -2230,6 +2234,21 @@ ix86_option_override_internal (bool main_args_p,
        if (((processor_alias_table[i].flags & PTA_PTWRITE) != 0)
            && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_PTWRITE))
          opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE;
+       if (((processor_alias_table[i].flags & PTA_WAITPKG) != 0)
+           && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_WAITPKG))
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG;
+       if (((processor_alias_table[i].flags & PTA_ENQCMD) != 0)
+           && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_ENQCMD))
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD;
+       if (((processor_alias_table[i].flags & PTA_CLDEMOTE) != 0)
+           && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_CLDEMOTE))
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE;
+       if (((processor_alias_table[i].flags & PTA_SERIALIZE) != 0)
+           && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_SERIALIZE))
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE;
+       if (((processor_alias_table[i].flags & PTA_TSXLDTRK) != 0)
+           && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_TSXLDTRK))
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK;
 
        if ((processor_alias_table[i].flags
           & (PTA_PREFETCH_SSE | PTA_SSE)) != 0)

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d6b57562a5388160b704d02b3824d71cc6da5678..f4a8f1391fae7ce60e6d47b8c15899d23eae98ea 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -448,6 +448,8 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE)
 #define TARGET_TIGERLAKE (ix86_tune == PROCESSOR_TIGERLAKE)
 #define TARGET_COOPERLAKE (ix86_tune == PROCESSOR_COOPERLAKE)
+#define TARGET_SAPPHIRERAPIDS (ix86_tune == PROCESSOR_SAPPHIRERAPIDS)
+#define TARGET_ALDERLAKE (ix86_tune == PROCESSOR_ALDERLAKE)
 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2348,6 +2350,8 @@ enum processor_type
   PROCESSOR_CASCADELAKE,
   PROCESSOR_TIGERLAKE,
   PROCESSOR_COOPERLAKE,
+  PROCESSOR_SAPPHIRERAPIDS,
+  PROCESSOR_ALDERLAKE,
   PROCESSOR_INTEL,
   PROCESSOR_GEODE,
   PROCESSOR_K6,
@@ -2449,6 +2453,10 @@ const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11);
 const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 12);
 const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13);
 const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14);
+const wide_int_bitmask PTA_ENQCMD (0, HOST_WIDE_INT_1U << 15);
+const wide_int_bitmask PTA_CLDEMOTE (0, HOST_WIDE_INT_1U << 16);
+const wide_int_bitmask PTA_SERIALIZE (0, HOST_WIDE_INT_1U << 17);
+const wide_int_bitmask PTA_TSXLDTRK (0, HOST_WIDE_INT_1U << 18);
 
 const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
   | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
@@ -2480,6 +2488,11 @@ const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
   | PTA_WBNOINVD | PTA_CLWB;
 const wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
   | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT;
+const wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI
+  | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_ENQCMD | PTA_CLDEMOTE
+  | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK;
+const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE | PTA_PTWRITE
+  | PTA_WAITPKG | PTA_SERIALIZE;
 const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
   | PTA_AVX512F | PTA_AVX512CD;
 const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index d1510dd3f367a25212b26d1831b156554a127f29..c800b741acf423197a0245d4e08ecc7f8694ba6c 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22256,6 +22256,12 @@ Intel Core i7 Tigerlake CPU.
 @item cooperlake
 Intel Core i7 Cooperlake CPU.
 
+@item sapphirerapids
+Intel Core i7 sapphirerapids CPU.
+
+@item alderlake
+Intel Core i7 Alderlake CPU.
+
 @item bonnell
 Intel Atom Bonnell CPU.
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f4fc303e7211e17165506bdf74e1168bafdb1928..09bcc5b0f78e69fe138a88fc3591505b58442099 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -29089,6 +29089,19 @@ RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
 VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and  AVX512VP2INTERSECT instruction
 set support.
 
+@item sapphirerapids
+Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
+FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES,
+AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16,
+MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
+SERIALIZE and TSXLDTRK instruction set support.
+
+@item alderlake
+Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, CLDEMOTE,
+PTWRITE, WAITPKG and SERIALIZE instruction set support.
+
 @item k6
 AMD K6 CPU with MMX instruction set support.
 

diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C
index 422b9cd684269d054d8edc4ae68fe1b02189c90f..9b29a1a3e1a8c10146fae2f6bcf183d4976f538c 100644 (file)
--- a/gcc/testsuite/g++.target/i386/mv16.C
+++ b/gcc/testsuite/g++.target/i386/mv16.C
@@ -80,6 +80,14 @@ int __attribute__ ((target("arch=cooperlake"))) foo () {
   return 21;
 }
 
+int __attribute__ ((target("arch=sapphirerapids"))) foo () {
+  return 22;
+}
+
+int __attribute__ ((target("arch=alderlake"))) foo () {
+  return 23;
+}
+
 int main ()
 {
   int val = foo ();
@@ -112,6 +120,10 @@ int main ()
     assert (val == 20);
   else if (__builtin_cpu_is ("cooperlake"))
     assert (val == 21);
+  else if (__builtin_cpu_is ("sapphirerapids"))
+    assert (val == 22);
+  else if (__builtin_cpu_is ("alderlake"))
+    assert (val == 23);
   else
     assert (val == 0);
 

diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 9fe4a21984b55b5d9b6925b5da3889a57680dc07..94ffbb64c75bb226ecf70cd824b43f44b773a023 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -163,6 +163,8 @@ extern void test_arch_icelake_server (void) __attribute__((__target__("arch=icel
 extern void test_arch_cascadelake (void)       __attribute__((__target__("arch=cascadelake")));
 extern void test_arch_tigerlake (void)          __attribute__((__target__("arch=tigerlake")));
 extern void test_arch_cooperlake (void)         __attribute__((__target__("arch=cooperlake")));
+extern void test_arch_sapphirerapids (void)    __attribute__((__target__("arch=sapphirerapids")));
+extern void test_arch_alderlake (void)          __attribute__((__target__("arch=alderlake")));
 extern void test_arch_k8 (void)                        __attribute__((__target__("arch=k8")));
 extern void test_arch_k8_sse3 (void)           __attribute__((__target__("arch=k8-sse3")));
 extern void test_arch_opteron (void)           __attribute__((__target__("arch=opteron")));