MIPS: Build vtophys in SE mode.

diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index c842c5507cc4c1f0090c104563949afffdd69126..282845f0d9b8c8ddbc6a32dbaa3dc41a85a17e70 100644 (file)
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -33,14 +33,15 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'mips':
+    Source('dsp.cc')
     Source('faults.cc')
     Source('interrupts.cc')
     Source('isa.cc')
-    Source('tlb.cc')
     Source('pagetable.cc')
-    Source('utility.cc')
-    Source('dsp.cc')
     Source('remote_gdb.cc')
+    Source('tlb.cc')
+    Source('utility.cc')
+    Source('vtophys.cc')
 
     SimObject('MipsInterrupts.py')
     DebugFlag('MipsPRA')
@@ -50,7 +51,6 @@ if env['TARGET_ISA'] == 'mips':
         SimObject('MipsSystem.py')
         Source('idle_event.cc')
         Source('mips_core_specific.cc')
-        Source('vtophys.cc')
         Source('system.cc')
         Source('stacktrace.cc')
         Source('linux/system.cc')

diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index 08e1a1e1c7fc6445ea925ceb1214bc67017e40f8..c6a317df893162c16ef7b6c2738530be6a14b8cc 100755 (executable)
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -37,6 +37,7 @@
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/VtoPhys.hh"
 #include "mem/vport.hh"
 
 using namespace std;
@@ -45,25 +46,13 @@ using namespace MipsISA;
 Addr
 MipsISA::vtophys(Addr vaddr)
 {
-    Addr paddr = 0;
-    if (MipsISA::IsUSeg(vaddr))
-        DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
-    else if (MipsISA::IsKSeg0(vaddr))
-        paddr = MipsISA::KSeg02Phys(vaddr);
-    else if(MipsISA::IsKSeg1(vaddr))
-        paddr = MipsISA::KSeg12Phys(vaddr);
-    else
-        panic("vtophys: ptbr is not set on "
-                "virtual lookup for vaddr %#x", vaddr);
-
-    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
-    return paddr;
+    fatal("VTOPHYS: Unimplemented on MIPS\n");
+    return 0;
 }
 
 Addr
 MipsISA::vtophys(ThreadContext *tc, Addr addr)
 {
-  fatal("VTOPHYS: Unimplemented on MIPS\n");
+    fatal("VTOPHYS: Unimplemented on MIPS\n");
 }
 

diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 5ecc30b1f1200ec78106268a0d7aedf97484d421..37a7378a83c862c3318585bbf4e3668ef7026ab0 100644 (file)
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -41,24 +41,6 @@ class ThreadContext;
 class FunctionalPort;
 
 namespace MipsISA {
-    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
-    // User Virtual
-    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
-
-    inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
-
-    inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
-
-    inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
-
-    inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
-
-    inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
-
-    inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
-
-
     Addr vtophys(Addr vaddr);
     Addr vtophys(ThreadContext *tc, Addr vaddr);