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 List of things that need more fleshed out bug reports:
 
 * Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG
+* Memory bus/L1/L2 Cache documentation  (bug #397)
 * Bperm tutorial
 * Bugseverywhere (or also https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go)
 * Competition to LS: Skywater 130nm production-ready PDK gets opensourced (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html)
-* Memory bus/L1/L2 Cache documentation  (bug #397)
+
 * Scoreboard documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
 * LDST documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
 * Follow up with graphics engineers, esp ones Yehowshua has already reached out to (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html)