radv: emit correct last export when Z/stencil export is enabled

I was getting a random GPU hang in the renderpass simple tests,
it turns out sometimes radv emitted the wrong thing "last".

This fixes the logic to emit Z/stencil last if they occur,
and not mark a color output as last. Also this relies on the
Z/STENCIL being the first two fragment outputs, which they are
so yay.

Fixes: dEQP-VK.renderpass.simple.color_depth (random hangs)
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 745baae01e362307926e2004ea3a79dcb96f1f85..8d364e68141135cdfa38b108158406ba9d3efc64 100644 (file)
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4353,12 +4353,10 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx,
 
        for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
                LLVMValueRef values[4];
-               bool last;
+
                if (!(ctx->output_mask & (1ull << i)))
                        continue;
 
-               last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
-
                if (i == FRAG_RESULT_DEPTH) {
                        ctx->shader_info->fs.writes_z = true;
                        depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
@@ -4368,10 +4366,14 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx,
                        stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
                                                              ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
                } else {
+                       bool last = false;
                        for (unsigned j = 0; j < 4; j++)
                                values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
                                                                        ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
 
+                       if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
+                               last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
+
                        si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
                        index++;
                }