etnaviv: GC7000: No RS align when using BLT

RS align is not necessary and might even be harmful when using the BLT
engine for blitting.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c
index ffdade9f09ee8d764982d58c93de16b36ff038ef..d70152e082dd235e20b6fc1f2cbc9960bae7d943 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -215,9 +215,11 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
    if (!util_format_is_compressed(templat->format)) {
       /* If we have the TEXTURE_HALIGN feature, we can always align to the
        * resolve engine's width.  If not, we must not align resources used
-       * only for textures. */
-      bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
-                      !etna_resource_sampler_only(templat);
+       * only for textures. If this GPU uses the BLT engine, never do RS align.
+       */
+      bool rs_align = screen->specs.use_blt ? false : (
+                         VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
+                         !etna_resource_sampler_only(templat));
       etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX,
                            &paddingY, &halign);
       assert(paddingX && paddingY);
@@ -228,7 +230,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
       paddingY = 1;
    }
 
-   if (templat->target != PIPE_BUFFER)
+   if (!screen->specs.use_blt && templat->target != PIPE_BUFFER)
       etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, &paddingY);
 
    if (templat->bind & PIPE_BIND_SCANOUT) {
@@ -237,7 +239,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
       struct winsys_handle handle;
 
       /* pad scanout buffer size to be compatible with the RS */
-      if (modifier == DRM_FORMAT_MOD_LINEAR)
+      if (!screen->specs.use_blt && modifier == DRM_FORMAT_MOD_LINEAR)
          etna_adjust_rs_align(screen->specs.pixel_pipes, &paddingX, &paddingY);
 
       scanout_templat.width0 = align(scanout_templat.width0, paddingX);
@@ -520,7 +522,8 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
                         VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN),
                         &paddingX, &paddingY, &rsc->halign);
 
-   etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, &paddingY);
+   if (!screen->specs.use_blt)
+      etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, &paddingY);
    level->padded_width = align(level->width, paddingX);
    level->padded_height = align(level->height, paddingY);
 

diff --git a/src/gallium/drivers/etnaviv/etnaviv_surface.c b/src/gallium/drivers/etnaviv/etnaviv_surface.c
index 4b95f6575a4517b35b8028a931d148b5d20a17c3..442957380082f8b1d1c8e192e4679f2a3e952188 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_surface.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_surface.c
@@ -116,26 +116,29 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
       surf->ts_reloc.offset = surf->surf.ts_offset;
       surf->ts_reloc.flags = 0;
 
-      /* This (ab)uses the RS as a plain buffer memset().
-       * Currently uses a fixed row size of 64 bytes. Some benchmarking with
-       * different sizes may be in order. */
-      struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
-      etna_compile_rs_state(ctx, &surf->clear_command, &(struct rs_state) {
-         .source_format = RS_FORMAT_A8R8G8B8,
-         .dest_format = RS_FORMAT_A8R8G8B8,
-         .dest = ts_bo,
-         .dest_offset = surf->surf.ts_offset,
-         .dest_stride = 0x40,
-         .dest_tiling = ETNA_LAYOUT_TILED,
-         .dither = {0xffffffff, 0xffffffff},
-         .width = 16,
-         .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
-         .clear_value = {ctx->specs.ts_clear_value},
-         .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
-         .clear_bits = 0xffff
-      });
+      if (!ctx->specs.use_blt) {
+         /* This (ab)uses the RS as a plain buffer memset().
+          * Currently uses a fixed row size of 64 bytes. Some benchmarking with
+          * different sizes may be in order. */
+         struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
+         etna_compile_rs_state(ctx, &surf->clear_command, &(struct rs_state) {
+            .source_format = RS_FORMAT_A8R8G8B8,
+            .dest_format = RS_FORMAT_A8R8G8B8,
+            .dest = ts_bo,
+            .dest_offset = surf->surf.ts_offset,
+            .dest_stride = 0x40,
+            .dest_tiling = ETNA_LAYOUT_TILED,
+            .dither = {0xffffffff, 0xffffffff},
+            .width = 16,
+            .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
+            .clear_value = {ctx->specs.ts_clear_value},
+            .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
+            .clear_bits = 0xffff
+         });
+      }
    } else {
-      etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
+      if (!ctx->specs.use_blt)
+         etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
    }
 
    return &surf->base;

diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
index aaaa1e61efe34558ab54e3d5e6ad72ec02fea5da..30ae3bfc39dda93325c10b2c078c318b75a5e240 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
@@ -214,27 +214,29 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc,
          return NULL;
       }
 
-      /* Need to align the transfer region to satisfy RS restrictions, as we
-       * really want to hit the RS blit path here.
-       */
-      unsigned w_align, h_align;
-
-      if (rsc->layout & ETNA_LAYOUT_BIT_SUPER) {
-         w_align = h_align = 64;
-      } else {
-         w_align = ETNA_RS_WIDTH_MASK + 1;
-         h_align = ETNA_RS_HEIGHT_MASK + 1;
+      if (!ctx->specs.use_blt) {
+         /* Need to align the transfer region to satisfy RS restrictions, as we
+          * really want to hit the RS blit path here.
+          */
+         unsigned w_align, h_align;
+
+         if (rsc->layout & ETNA_LAYOUT_BIT_SUPER) {
+            w_align = h_align = 64;
+         } else {
+            w_align = ETNA_RS_WIDTH_MASK + 1;
+            h_align = ETNA_RS_HEIGHT_MASK + 1;
+         }
+         h_align *= ctx->screen->specs.pixel_pipes;
+
+         ptrans->box.width += ptrans->box.x & (w_align - 1);
+         ptrans->box.x = ptrans->box.x & ~(w_align - 1);
+         ptrans->box.width = align(ptrans->box.width, (ETNA_RS_WIDTH_MASK + 1));
+         ptrans->box.height += ptrans->box.y & (h_align - 1);
+         ptrans->box.y = ptrans->box.y & ~(h_align - 1);
+         ptrans->box.height = align(ptrans->box.height,
+                                    (ETNA_RS_HEIGHT_MASK + 1) *
+                                     ctx->screen->specs.pixel_pipes);
       }
-      h_align *= ctx->screen->specs.pixel_pipes;
-
-      ptrans->box.width += ptrans->box.x & (w_align - 1);
-      ptrans->box.x = ptrans->box.x & ~(w_align - 1);
-      ptrans->box.width = align(ptrans->box.width, (ETNA_RS_WIDTH_MASK + 1));
-      ptrans->box.height += ptrans->box.y & (h_align - 1);
-      ptrans->box.y = ptrans->box.y & ~(h_align - 1);
-      ptrans->box.height = align(ptrans->box.height,
-                                 (ETNA_RS_HEIGHT_MASK + 1) *
-                                  ctx->screen->specs.pixel_pipes);
 
       if (!(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE))
          etna_copy_resource_box(pctx, trans->rsc, prsc, level, &ptrans->box);