[sim] more fp<->int fixes

diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 638a5eca630b1f6d4b7b4dbb49ad08eb38a1cb81..52abd7597125b82d88418351fbd7b3cee3e0f737 100644 (file)
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f64(RS1);
+FRD = i32_to_f64((int32_t)RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 2757790f1500d43986cfcf0970ec006f80d256d7..61a8a788a34d41e6aa79e943b35cb09f5dc89993 100644 (file)
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f64(RS1);
+FRD = ui32_to_f64((uint32_t)RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 12b1e733f3031bb5e89ea4f3df235f520a3b147c..dedebb549b49cdbedf424e384ba4c3164d2bf672 100644 (file)
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f32(RS1);
+FRD = i32_to_f32((int32_t)RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index 4c53c01ed02d5786fa61f5e67fef466676ce0bdf..abb782c38126d777928907cc3ba724215121ed49 100644 (file)
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f32(RS1);
+FRD = ui32_to_f32((uint32_t)RS1);
 set_fp_exceptions;