ARM: When an instruction is intentionally undefined, fault on it.

diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa
index fda04363efbda7fc6cade292d7ba0377e2f0ac67..231796281292bc1c098eb33dc40adee687302bc2 100644 (file)
--- a/src/arch/arm/isa/decoder/thumb.isa
+++ b/src/arch/arm/isa/decoder/thumb.isa
@@ -102,7 +102,7 @@
                 0x3: WarnUnimpl::Advanced_SIMD();
                 default: decode LTCOPROC {
                     0xa, 0xb: decode HTOPCODE_9_4 {
-                        0x00: WarnUnimpl::undefined();
+                        0x00: Unknown::undefined();
                         0x04: WarnUnimpl::mcrr(); // mcrr2
                         0x05: WarnUnimpl::mrrc(); // mrrc2
                         0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
@@ -116,7 +116,7 @@
                             }
                     }
                     default: decode HTOPCODE_9_5 {
-                        0x00: WarnUnimpl::undefined();
+                        0x00: Unknown::undefined();
                         0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
                         0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
                         0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
@@ -142,7 +142,7 @@
                     0x0: LoadByteMemoryHints::loadByteMemoryHints();
                     0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints();
                     0x2: Thumb32LoadWord::thumb32LoadWord();
-                    0x3: WarnUnimpl::undefined();
+                    0x3: Unknown::undefined();
                 }
             }
             0x1: decode HTOPCODE_8_7 {
@@ -170,7 +170,7 @@
                 0x3: WarnUnimpl::Advanced_SIMD();
                 default: decode LTCOPROC {
                     0xa, 0xb: decode HTOPCODE_9_4 {
-                        0x00: WarnUnimpl::undefined();
+                        0x00: Unknown::undefined();
                         0x04: WarnUnimpl::mcrr(); // mcrr2
                         0x05: WarnUnimpl::mrrc(); // mrrc2
                         0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
@@ -184,7 +184,7 @@
                             }
                     }
                     default: decode HTOPCODE_9_5 {
-                        0x00: WarnUnimpl::undefined();
+                        0x00: Unknown::undefined();
                         0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
                         0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
                         0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:

diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 07f39b1294b836179a22dc7d00b5ddd4183d16a9..458a9d3fdc194994d8755e6b1d744ed0b8cac4c6 100644 (file)
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -104,7 +104,7 @@ def format Thumb16CondBranchAndSvc() {{
             return new Svc(machInst);
         } else {
             // This space will not be allocated in the future.
-            return new WarnUnimplemented("unimplemented", machInst);
+            return new Unknown(machInst);
         }
     '''
 }};
@@ -124,8 +124,8 @@ def format Thumb32BranchesAndMiscCtrl() {{
           case 0x0:
             if (op == 127) {
                 if (op1 & 0x2) {
-                    // Permanentl undefined.
-                    return new WarnUnimplemented("undefined", machInst);
+                    // Permanently undefined.
+                    return new Unknown(machInst);
                 } else {
                     return new WarnUnimplemented("smc", machInst);
                 }