ilo_3d_pipeline_emit_flush(hw3d->pipeline);
/* don't know why */
- if (ilo->gen >= ILO_GEN(7))
+ if (ilo->dev->gen >= ILO_GEN(7))
ilo_cp_flush(hw3d->cp);
}
ILO_DEBUG_NOCACHE = 1 << 9,
};
+struct ilo_dev_info {
+ /* these mirror intel_winsys_info */
+ int devid;
+ bool has_llc;
+ bool has_gen7_sol_reset;
+
+ int gen;
+ int gt;
+};
+
extern int ilo_debug;
/**
return NULL;
ilo->winsys = is->winsys;
- ilo->devid = is->devid;
- ilo->gen = is->gen;
-
- if (IS_SNB_GT1(ilo->devid) ||
- IS_IVB_GT1(ilo->devid) ||
- IS_HSW_GT1(ilo->devid) ||
- IS_BAYTRAIL(ilo->devid))
- ilo->gt = 1;
- else if (IS_SNB_GT2(ilo->devid) ||
- IS_IVB_GT2(ilo->devid) ||
- IS_HSW_GT2(ilo->devid))
- ilo->gt = 2;
- else
- ilo->gt = 0;
+ ilo->dev = &is->dev;
/* stolen from classic i965 */
/* WM maximum threads is number of EUs times number of threads per EU. */
- if (ilo->gen >= ILO_GEN(7)) {
- if (ilo->gt == 1) {
+ if (ilo->dev->gen >= ILO_GEN(7)) {
+ if (ilo->dev->gt == 1) {
ilo->max_wm_threads = 48;
ilo->max_vs_threads = 36;
ilo->max_gs_threads = 36;
ilo->urb.size = 128;
ilo->urb.max_vs_entries = 512;
ilo->urb.max_gs_entries = 192;
- } else if (ilo->gt == 2) {
+ } else if (ilo->dev->gt == 2) {
ilo->max_wm_threads = 172;
ilo->max_vs_threads = 128;
ilo->max_gs_threads = 128;
} else {
assert(!"Unknown gen7 device.");
}
- } else if (ilo->gen == ILO_GEN(6)) {
- if (ilo->gt == 2) {
+ } else if (ilo->dev->gen == ILO_GEN(6)) {
+ if (ilo->dev->gt == 2) {
ilo->max_wm_threads = 80;
ilo->max_vs_threads = 60;
ilo->max_gs_threads = 60;
}
}
- ilo->cp = ilo_cp_create(ilo->winsys, is->has_llc);
+ ilo->cp = ilo_cp_create(ilo->winsys, is->dev.has_llc);
ilo->shader_cache = ilo_shader_cache_create(ilo->winsys);
if (ilo->cp)
- ilo->hw3d = ilo_3d_create(ilo->cp, ilo->gen, ilo->gt);
+ ilo->hw3d = ilo_3d_create(ilo->cp, ilo->dev->gen, ilo->dev->gt);
if (!ilo->cp || !ilo->shader_cache || !ilo->hw3d) {
ilo_context_destroy(&ilo->base);
struct pipe_context base;
struct intel_winsys *winsys;
- int devid;
- int gen;
- int gt;
+ struct ilo_dev_info *dev;
int max_vs_threads;
int max_gs_threads;
unsigned bindings)
{
struct ilo_screen *is = ilo_screen(screen);
- const int gen = ILO_GEN_GET_MAJOR(is->gen * 10);
+ const int gen = ILO_GEN_GET_MAJOR(is->dev.gen * 10);
const struct surface_format_info *info;
unsigned bind;
/* prefer map() when there is the last-level cache */
if (res->tiling == INTEL_TILING_NONE &&
- (is->has_llc || (usage & PIPE_TRANSFER_READ)))
+ (is->dev.has_llc || (usage & PIPE_TRANSFER_READ)))
err = res->bo->map(res->bo, (usage & PIPE_TRANSFER_WRITE));
else
err = res->bo->map_gtt(res->bo);
info->align_j = info->block_height;
}
else if (util_format_is_depth_or_stencil(templ->format)) {
- if (is->gen >= ILO_GEN(7)) {
+ if (is->dev.gen >= ILO_GEN(7)) {
switch (templ->format) {
case PIPE_FORMAT_Z16_UNORM:
info->align_i = 8;
}
else {
const bool valign_4 = (templ->nr_samples > 1) ||
- (is->gen >= ILO_GEN(7) &&
+ (is->dev.gen >= ILO_GEN(7) &&
(templ->bind & PIPE_BIND_RENDER_TARGET) &&
tiling == INTEL_TILING_Y);
* res->slice_offsets, we do not need to divide QPitch by 4.
*/
info->qpitch = h0 + h1 +
- ((is->gen >= ILO_GEN(7)) ? 12 : 11) * info->align_j;
+ ((is->dev.gen >= ILO_GEN(7)) ? 12 : 11) * info->align_j;
- if (is->gen == ILO_GEN(6) && templ->nr_samples > 1 &&
+ if (is->dev.gen == ILO_GEN(6) && templ->nr_samples > 1 &&
templ->height0 % 4 == 1)
info->qpitch += 4;
}
case PIPE_CAP_SM3:
return true;
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
- if (is->gen >= ILO_GEN(7))
+ if (is->dev.gen >= ILO_GEN(7))
return 0; /* TODO */
return ILO_MAX_SO_BUFFERS;
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_INDEP_BLEND_FUNC:
return true;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return (is->gen >= ILO_GEN(7)) ? 2048 : 512;
+ return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
const char *chipset;
/* stolen from classic i965 */
- switch (is->devid) {
+ switch (is->dev.devid) {
case PCI_CHIP_SANDYBRIDGE_GT1:
case PCI_CHIP_SANDYBRIDGE_GT2:
case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
FREE(is);
}
+static bool
+init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
+{
+ dev->devid = info->devid;
+ dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
+ dev->has_llc = info->has_llc;
+
+ if (IS_HASWELL(info->devid)) {
+ dev->gen = ILO_GEN(7.5);
+
+ if (IS_HSW_GT2(info->devid))
+ dev->gt = 2;
+ else
+ dev->gt = 1;
+ }
+ else if (IS_GEN7(info->devid)) {
+ dev->gen = ILO_GEN(7);
+
+ if (IS_IVB_GT2(info->devid))
+ dev->gt = 2;
+ else
+ dev->gt = 1;
+ }
+ else if (IS_GEN6(info->devid)) {
+ dev->gen = ILO_GEN(6);
+
+ if (IS_SNB_GT2(info->devid))
+ dev->gt = 2;
+ else
+ dev->gt = 1;
+ }
+ else {
+ ilo_err("unknown GPU generation\n");
+ return false;
+ }
+
+ return true;
+}
+
struct pipe_screen *
ilo_screen_create(struct intel_winsys *ws)
{
is->winsys = ws;
info = is->winsys->get_info(is->winsys);
-
- is->devid = info->devid;
- if (IS_GEN7(info->devid)) {
- is->gen = ILO_GEN(7);
- }
- else if (IS_GEN6(info->devid)) {
- is->gen = ILO_GEN(6);
- }
- else {
- ilo_err("unknown GPU generation\n");
+ if (!init_dev(&is->dev, info)) {
FREE(is);
return NULL;
}
- is->has_llc = info->has_llc;
-
util_format_s3tc_init();
is->base.destroy = ilo_screen_destroy;
struct pipe_screen base;
struct intel_winsys *winsys;
- int devid;
- int gen;
-
- bool has_llc;
+ struct ilo_dev_info dev;
};
static inline struct ilo_screen *
return NULL;
state->info.type = type;
- state->info.gen = ilo->gen;
+ state->info.gen = ilo->dev->gen;
if (type == PIPE_SHADER_COMPUTE) {
const struct pipe_compute_state *c =