2002-02-28 Chris Demetriou <cgd@broadcom.com>

        * mips.igen (DSRA32, DSRAV): Fix order of arguments in
        instruction-printing string.
        (LWU): Use '64' as the filter flag.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index e3ca0ec04ac5f9045cd42178fdbb48f0e405e6fe..cb69ddb74c2c01da92170ee1ae2ac8ed7fd68e52 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,9 @@
+2002-02-28  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.igen (DSRA32, DSRAV): Fix order of arguments in
+       instruction-printing string.
+       (LWU): Use '64' as the filter flag.
+
 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 
        * mips.igen (SDXC1): Fix instruction-printing string.

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index eb511194591c595b062aae5f09849b62bad7a44a..02ae7607835ee8310f183ec7c2c5925e3fd856ba 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1248,7 +1248,7 @@
 
 
 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
-"dsra32 r<RT>, r<RD>, <SHIFT>"
+"dsra32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
 *mipsV:
@@ -1270,7 +1270,7 @@
 }
 
 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
-"dsrav r<RT>, r<RD>, r<RS>"
+"dsrav r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
 *mipsV:
@@ -1824,7 +1824,7 @@
 }
 
 
-100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
+100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
 "lwu r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV: