power_insn: drop registers remapping hack

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index b27fdb9f0d5c09123e1ec44a591a0b926aeb9ed0..486d1d655198d44eba8cc4e01df7a2fb1a441934 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -619,15 +619,6 @@ class Operands:
             "addpcis": {"D": DOperandDX},
             "fishmv": {"D": DOperandDX},
             "fmvis": {"D": DOperandDX},
-
-            # FIXME: these instructions are broken according to the specs.
-            # The operands in the assembly syntax are FRT,FRA,FRC,FRB.
-            # The real assembly order, however, is FRT,FRA,FRB,FRC.
-            # The legacy assembler placed operands in syntax order.
-            #"ffmadds": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC},
-            #"ffmadds.": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC},
-            #"fdmadds": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC},
-            #"fdmadds.": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC},
         }
         custom_fields = {
             "SVi": NonZeroOperand,
@@ -1371,28 +1362,6 @@ class FPROperand(SimpleRegisterOperand):
             style=style, indent=indent)
 
 
-class RedirectedOperand(DynamicOperand):
-    def __init__(self, record, name, target):
-        self.__target = target
-        return super().__init__(record=record, name=name)
-
-    @cached_property
-    def span(self):
-        print(f"{self.record.name}: {self.name} => "
-              f"{self.__target}", file=_sys.stderr)
-        return self.record.fields[self.__target]
-
-
-class FMAOperandFRB(RedirectedOperand, FPROperand):
-    def __init__(self, record, name):
-        return super().__init__(record=record, name=name, target="FRC")
-
-
-class FMAOperandFRC(RedirectedOperand, FPROperand):
-    def __init__(self, record, name):
-        return super().__init__(record=record, name=name, target="FRB")
-
-
 class FPRPairOperand(FPROperand):
     pass