[ARM/FDPIC v6 12/24] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp

We call __aeabi_read_tp() to get the thread pointer. Since this is a
function call, we have to restore the FDPIC register afterwards.

2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
	Mickaël Guêné <mickael.guene@st.com>

	gcc/
	* config/arm/arm.c (arm_load_tp): Add FDPIC support.
	* config/arm/arm.md (FDPIC_REGNUM): New constant.
	(load_tp_soft_fdpic): New pattern.
	(load_tp_soft): Disable in FDPIC mode.

Co-Authored-By: Mickaël Guêné <mickael.guene@st.com>
From-SVN: r275574

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eff014123baa160776b32958a1f7c54b5dfe4387..afe73b59f5d471ec22b4bc2126c7d9d76367c7ba 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,7 +1,14 @@
 2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
        Mickaël Guêné <mickael.guene@st.com>
 
-       gcc/
+       * config/arm/arm.c (arm_load_tp): Add FDPIC support.
+       * config/arm/arm.md (FDPIC_REGNUM): New constant.
+       (load_tp_soft_fdpic): New pattern.
+       (load_tp_soft): Disable in FDPIC mode.
+
+2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
+       Mickaël Guêné <mickael.guene@st.com>
+
        * config/arm/arm.c (tls_reloc): Add TLS_GD32_FDPIC,
        TLS_LDM32_FDPIC and TLS_IE32_FDPIC.
        (arm_call_tls_get_addr): Add FDPIC support.
@@ -11,7 +18,6 @@
 2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
        Mickaël Guêné <mickael.guene@st.com>
 
-       gcc/
        * config/arm/arm.c (arm_asm_trampoline_template): Add FDPIC
        support.
        (arm_trampoline_init): Likewise.

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 5f1d2d41795733339626009f81e79d9ecf0791f4..c452771f473aeb8b074f4f9a05f4c040e15db614 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8685,7 +8685,18 @@ arm_load_tp (rtx target)
 
       rtx tmp;
 
-      emit_insn (gen_load_tp_soft ());
+      if (TARGET_FDPIC)
+       {
+         rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
+         rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM);
+
+         emit_insn (gen_load_tp_soft_fdpic ());
+
+         /* Restore r9.  */
+         emit_insn (gen_restore_pic_register_after_call(fdpic_reg, initial_fdpic_reg));
+       }
+      else
+       emit_insn (gen_load_tp_soft ());
 
       tmp = gen_rtx_REG (SImode, R0_REGNUM);
       emit_move_insn (target, tmp);

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 027febbaebb24c5e377d3e0cdd7d387e2037ebe1..918271d7ad5e263001a342d63f3ab07c076e3a47 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -31,6 +31,7 @@
   [(R0_REGNUM         0)       ; First CORE register
    (R1_REGNUM        1)        ; Second CORE register
    (R4_REGNUM        4)        ; Fifth CORE register
+   (FDPIC_REGNUM      9)       ; FDPIC register
    (IP_REGNUM       12)        ; Scratch register
    (SP_REGNUM       13)        ; Stack pointer
    (LR_REGNUM        14)       ; Return address register
@@ -11164,13 +11165,26 @@
    (set_attr "type" "mrs")]
 )
 
+;; Doesn't clobber R1-R3.  Must use r0 for the first operand.
+(define_insn "load_tp_soft_fdpic"
+  [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
+   (clobber (reg:SI FDPIC_REGNUM))
+   (clobber (reg:SI LR_REGNUM))
+   (clobber (reg:SI IP_REGNUM))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_SOFT_TP && TARGET_FDPIC"
+  "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
+  [(set_attr "conds" "clob")
+   (set_attr "type" "branch")]
+)
+
 ;; Doesn't clobber R1-R3.  Must use r0 for the first operand.
 (define_insn "load_tp_soft"
   [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
    (clobber (reg:SI LR_REGNUM))
    (clobber (reg:SI IP_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_SOFT_TP"
+  "TARGET_SOFT_TP && !TARGET_FDPIC"
   "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
   [(set_attr "conds" "clob")
    (set_attr "type" "branch")]