[system.cpu]
type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
+children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
smtROBThreshold=100
squashWidth=8
system=system
+tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
[system.cpu.fuPool.FUList0]
type=FUDesc
-children=opList0
+children=opList
count=6
-opList=system.cpu.fuPool.FUList0.opList0
+opList=system.cpu.fuPool.FUList0.opList
-[system.cpu.fuPool.FUList0.opList0]
+[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList4.opList0
+opList=system.cpu.fuPool.FUList4.opList
-[system.cpu.fuPool.FUList4.opList0]
+[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
[system.cpu.fuPool.FUList5]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList5.opList0
+opList=system.cpu.fuPool.FUList5.opList
-[system.cpu.fuPool.FUList5.opList0]
+[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0
+children=opList
count=1
-opList=system.cpu.fuPool.FUList7.opList0
+opList=system.cpu.fuPool.FUList7.opList
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 522 # Number of BTB hits
-global.BPredUnit.BTBLookups 1584 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1088 # Number of conditional branches predicted
-global.BPredUnit.lookups 1837 # Number of BP lookups
-global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target.
-host_inst_rate 39303 # Simulator instruction rate (inst/s)
-host_mem_usage 153768 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
-host_tick_rate 32016268 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 127 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 1874 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1142 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 543 # Number of BTB hits
+global.BPredUnit.BTBLookups 1720 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1175 # Number of conditional branches predicted
+global.BPredUnit.lookups 2025 # Number of BP lookups
+global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target.
+host_inst_rate 29843 # Simulator instruction rate (inst/s)
+host_mem_usage 154572 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
+host_tick_rate 22095832 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 133 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 1967 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1200 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000005 # Number of seconds simulated
-sim_ticks 4589500 # Number of ticks simulated
+sim_seconds 0.000004 # Number of seconds simulated
+sim_ticks 4170500 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 8521
+system.cpu.commit.COM:committed_per_cycle.samples 7614
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 6200 7276.14%
- 1 1160 1361.34%
- 2 469 550.40%
- 3 177 207.72%
- 4 131 153.74%
- 5 98 115.01%
- 6 109 127.92%
- 7 73 85.67%
- 8 104 122.05%
+ 0 5315 6980.56%
+ 1 1182 1552.40%
+ 2 399 524.03%
+ 3 192 252.17%
+ 4 125 164.17%
+ 5 99 130.02%
+ 6 130 170.74%
+ 7 67 88.00%
+ 8 105 137.90%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 349 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 3571 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 3957 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.636315 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.636315 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1470 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5932.330827 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5380 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1337 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 789000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.090476 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 538000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.068027 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4504.373178 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1545000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
+system.cpu.cpi 1.483372 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.483372 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1487 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 8188.118812 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5495.049505 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1386 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 827000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.067922 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 555000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.067922 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 561 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 18316.091954 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5068.965517 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 474 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 1593500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.155080 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 251 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 441000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.155080 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 10.439306 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 10.770115 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2282 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4903.361345 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 5268.786127 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1806 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 2334000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.208589 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 911500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.075811 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 2048 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 12875 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1860 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 2420500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.091797 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 996000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.091797 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2282 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4903.361345 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 5268.786127 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 2048 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 12875 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1806 # number of overall hits
-system.cpu.dcache.overall_miss_latency 2334000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.208589 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 476 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 911500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.075811 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 1860 # number of overall hits
+system.cpu.dcache.overall_miss_latency 2420500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.091797 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 188 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 285 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 996000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.091797 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 112.669258 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1806 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 112.600183 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1874 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 143 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 10466 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 1855 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 679 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:BlockedCycles 391 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 82 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 164 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 11387 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 5174 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2002 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 726 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 1837 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1469 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3456 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 11417 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.199652 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1469 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.240843 # Number of inst fetches per cycle
+system.cpu.fetch.Branches 2025 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1529 # Number of cache lines fetched
+system.cpu.fetch.Cycles 3690 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 212 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 12463 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 457 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.242777 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1529 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 820 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.494185 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 9201
+system.cpu.fetch.rateDist.samples 8341
system.cpu.fetch.rateDist.min_value 0
- 0 7216 7842.63%
- 1 168 182.59%
- 2 148 160.85%
- 3 136 147.81%
- 4 214 232.58%
- 5 138 149.98%
- 6 177 192.37%
- 7 95 103.25%
- 8 909 987.94%
+ 0 6181 7410.38%
+ 1 173 207.41%
+ 2 174 208.61%
+ 3 151 181.03%
+ 4 219 262.56%
+ 5 157 188.23%
+ 6 179 214.60%
+ 7 102 122.29%
+ 8 1005 1204.89%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1469 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5381.818182 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4530.448718 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1139 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1776000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.224643 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses
+system.cpu.icache.ReadReq_accesses 1511 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5621.019108 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4464.968153 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1197 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1765000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.207809 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 314 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1413500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.212389 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency 1402000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.207809 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.650641 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.812102 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1469 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5381.818182 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4530.448718 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1139 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1776000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.224643 # miss rate for demand accesses
-system.cpu.icache.demand_misses 330 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 1511 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5621.019108 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1197 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1765000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.207809 # miss rate for demand accesses
+system.cpu.icache.demand_misses 314 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1413500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.212389 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 1402000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.207809 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1469 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5381.818182 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4530.448718 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 1511 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5621.019108 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1139 # number of overall hits
-system.cpu.icache.overall_miss_latency 1776000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.224643 # miss rate for overall accesses
-system.cpu.icache.overall_misses 330 # number of overall misses
+system.cpu.icache.overall_hits 1197 # number of overall hits
+system.cpu.icache.overall_miss_latency 1765000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.207809 # miss rate for overall accesses
+system.cpu.icache.overall_misses 314 # number of overall misses
system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1413500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.212389 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 1402000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.207809 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 165.921810 # Cycle average of tags in use
-system.cpu.icache.total_refs 1139 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 167.838424 # Cycle average of tags in use
+system.cpu.icache.total_refs 1197 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 2474 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1144 # Number of branches executed
-system.cpu.iew.EXEC:nop 40 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.835018 # Inst execution rate
-system.cpu.iew.EXEC:refs 2519 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 977 # Number of stores executed
+system.cpu.idleCycles 1997 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1159 # Number of branches executed
+system.cpu.iew.EXEC:nop 43 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.933581 # Inst execution rate
+system.cpu.iew.EXEC:refs 2561 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 971 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5193 # num instructions consuming a value
-system.cpu.iew.WB:count 7387 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.742923 # average fanout of values written-back
+system.cpu.iew.WB:consumers 5329 # num instructions consuming a value
+system.cpu.iew.WB:count 7480 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.739351 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 3858 # num instructions producing a value
-system.cpu.iew.WB:rate 0.802848 # insts written-back per cycle
-system.cpu.iew.WB:sent 7452 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 373 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 3940 # num instructions producing a value
+system.cpu.iew.WB:rate 0.896775 # insts written-back per cycle
+system.cpu.iew.WB:sent 7559 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 402 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 1874 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 302 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1142 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9228 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 1542 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 7683 # Number of executed instructions
+system.cpu.iew.iewDispLoadInsts 1967 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1200 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9614 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1590 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 364 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 7787 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 679 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 70 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 895 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.611129 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.611129 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 7968 # Type of FU issued
+system.cpu.iew.lsq.thread.0.squashedLoads 988 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 388 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 70 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 115 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.674140 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.674140 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 8151 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 2 0.03% # Type of FU issued
- IntAlu 5314 66.69% # Type of FU issued
+ No_OpClass 2 0.02% # Type of FU issued
+ IntAlu 5422 66.52% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.03% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1659 20.82% # Type of FU issued
- MemWrite 990 12.42% # Type of FU issued
+ MemRead 1720 21.10% # Type of FU issued
+ MemWrite 1004 12.32% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013178 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 104 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.012759 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 70 66.67% # attempts to use FU when none available
- MemWrite 35 33.33% # attempts to use FU when none available
+ MemRead 70 67.31% # attempts to use FU when none available
+ MemWrite 34 32.69% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 9201
+system.cpu.iq.ISSUE:issued_per_cycle.samples 8341
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 5952 6468.86%
- 1 1111 1207.48%
- 2 928 1008.59%
- 3 433 470.60%
- 4 378 410.82%
- 5 251 272.80%
- 6 111 120.64%
- 7 27 29.34%
- 8 10 10.87%
+ 0 5104 6119.17%
+ 1 1084 1299.60%
+ 2 829 993.89%
+ 3 533 639.01%
+ 4 366 438.80%
+ 5 258 309.32%
+ 6 126 151.06%
+ 7 28 33.57%
+ 8 13 15.59%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.865993 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9166 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 7968 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3154 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.ISSUE:rate 0.977221 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9548 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8151 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 3578 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2035 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4644.927536 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2467.908903 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 2243500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1192000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses
+system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2360 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 3643.835616 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2643.835616 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 266000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 193000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3406.779661 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.779661 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1407000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.995181 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 994000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995181 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 3392.857143 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2392.857143 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 47500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 33500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4644.927536 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2467.908903 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2243500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 488 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3442.386831 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 1673000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995902 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 486 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1192000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 1187000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995902 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 486 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4644.927536 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2467.908903 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 488 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3442.386831 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2243500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 483 # number of overall misses
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 1673000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995902 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 486 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1192000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 1187000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995902 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 486 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 278.204751 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 223.758944 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 9201 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking
+system.cpu.numCycles 8341 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 6382 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 12837 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 10018 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 7477 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1754 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 679 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 3426 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IdleCycles 5339 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 13891 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 10852 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8114 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1888 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 726 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 102 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4063 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 272 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
-system.cpu.timesIdled 26 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:skidInsts 382 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Jun 21 2007 21:25:27
-M5 started Fri Jun 22 00:04:38 2007
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:12 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 4589500 because target called exit()
+Exiting @ tick 4170500 because target called exit()
[system.cpu]
type=AtomicSimpleCPU
-children=workload
+children=tracer workload
clock=500
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
---------- Begin Simulation Statistics ----------
-host_inst_rate 93019 # Simulator instruction rate (inst/s)
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 46199079 # Simulator tick rate (ticks/s)
+host_inst_rate 109073 # Simulator instruction rate (inst/s)
+host_mem_usage 148564 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 54123810 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
All Rights Reserved
-M5 compiled Jun 10 2007 14:06:20
-M5 started Sun Jun 10 14:22:34 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:12 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2820500 because target called exit()
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
---------- Begin Simulation Statistics ----------
-host_inst_rate 54390 # Simulator instruction rate (inst/s)
-host_seconds 0.10 # Real time elapsed on the host
-host_tick_rate 126525357 # Simulator tick rate (ticks/s)
+host_inst_rate 65923 # Simulator instruction rate (inst/s)
+host_mem_usage 154180 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 155349854 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13168000 # Number of ticks simulated
+sim_ticks 13359000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1022000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 949000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 1218000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 1131000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 2310000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 2506000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 2145000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 2327000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1626 # number of overall hits
-system.cpu.dcache.overall_miss_latency 2310000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 165 # number of overall misses
+system.cpu.dcache.overall_hits 1612 # number of overall hits
+system.cpu.dcache.overall_miss_latency 2506000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 179 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 2145000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 2327000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 103.640117 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 103.895955 # Cycle average of tags in use
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13960.288809 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 13992.779783 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12992.779783 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3867000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 3876000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 3590000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 3599000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13960.288809 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 13992.779783 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3867000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 3876000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 3590000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 3599000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13960.288809 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 13992.779783 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5366 # number of overall hits
-system.cpu.icache.overall_miss_latency 3867000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 3876000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
system.cpu.icache.overall_misses 277 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 3590000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 3599000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 129.241810 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 129.745202 # Cycle average of tags in use
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 876000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 5733000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4851000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 4416000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002825 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 5733000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 5292000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 5733000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_hits 1 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 5292000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 441 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 232.802947 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 179.464793 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 13168000 # number of cpu cycles simulated
+system.cpu.numCycles 13359000 # number of cpu cycles simulated
system.cpu.num_insts 5642 # Number of instructions executed
system.cpu.num_refs 1792 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
All Rights Reserved
-M5 compiled Jun 10 2007 14:06:20
-M5 started Sun Jun 10 14:22:35 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:13 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 13168000 because target called exit()
+Exiting @ tick 13359000 because target called exit()
[system.cpu]
type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
+children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
smtROBThreshold=100
squashWidth=8
system=system
+tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
[system.cpu.fuPool.FUList0]
type=FUDesc
-children=opList0
+children=opList
count=6
-opList=system.cpu.fuPool.FUList0.opList0
+opList=system.cpu.fuPool.FUList0.opList
-[system.cpu.fuPool.FUList0.opList0]
+[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList4.opList0
+opList=system.cpu.fuPool.FUList4.opList
-[system.cpu.fuPool.FUList4.opList0]
+[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
[system.cpu.fuPool.FUList5]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList5.opList0
+opList=system.cpu.fuPool.FUList5.opList
-[system.cpu.fuPool.FUList5.opList0]
+[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0
+children=opList
count=1
-opList=system.cpu.fuPool.FUList7.opList0
+opList=system.cpu.fuPool.FUList7.opList
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 132 # Number of BTB hits
-global.BPredUnit.BTBLookups 584 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 376 # Number of conditional branches predicted
-global.BPredUnit.lookups 738 # Number of BP lookups
-global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target.
-host_inst_rate 39805 # Simulator instruction rate (inst/s)
-host_mem_usage 153128 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 34110715 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads.
+global.BPredUnit.BTBHits 146 # Number of BTB hits
+global.BPredUnit.BTBLookups 613 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 393 # Number of conditional branches predicted
+global.BPredUnit.lookups 777 # Number of BP lookups
+global.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target.
+host_inst_rate 24407 # Simulator instruction rate (inst/s)
+host_mem_usage 153952 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 19202153 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 635 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 367 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
-sim_ticks 2055000 # Number of ticks simulated
+sim_ticks 1884000 # Number of ticks simulated
system.cpu.commit.COM:branches 396 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 33 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 3910
+system.cpu.commit.COM:committed_per_cycle.samples 3543
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 2950 7544.76%
- 1 266 680.31%
- 2 336 859.34%
- 3 131 335.04%
- 4 76 194.37%
- 5 65 166.24%
- 6 27 69.05%
- 7 18 46.04%
- 8 41 104.86%
+ 0 2580 7281.96%
+ 1 265 747.95%
+ 2 337 951.17%
+ 3 138 389.50%
+ 4 67 189.11%
+ 5 69 194.75%
+ 6 32 90.32%
+ 7 22 62.09%
+ 8 33 93.14%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 709 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1118 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 1.723083 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.723083 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5391.304348 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4669.491525 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 372000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses
+system.cpu.cpi 1.578969 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.578969 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 518 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 6583.333333 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4891.666667 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 395000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.115830 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 60 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 275500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 293500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.115830 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 60 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 239 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 14216.216216 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5202.702703 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 202 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 526000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.154812 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 55 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 192500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.154812 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 7.905882 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 5532.142857 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 774500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 401000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 757 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 9494.845361 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 660 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 921000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.128137 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 97 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 486000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.128137 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 97 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 5532.142857 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 757 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 9494.845361 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 668 # number of overall hits
-system.cpu.dcache.overall_miss_latency 774500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 140 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 401000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 660 # number of overall hits
+system.cpu.dcache.overall_miss_latency 921000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.128137 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 97 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 65 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 486000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.128137 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 97 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 51.873008 # Cycle average of tags in use
-system.cpu.dcache.total_refs 668 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 51.399169 # Cycle average of tags in use
+system.cpu.dcache.total_refs 672 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 771 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode
-system.cpu.fetch.Branches 738 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 654 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1444 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.179431 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.139071 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:BlockedCycles 87 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 125 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 4218 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 2648 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 808 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 777 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 686 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1528 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 107 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 4951 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.206155 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 686 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 299 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.313611 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 4113
+system.cpu.fetch.rateDist.samples 3769
system.cpu.fetch.rateDist.min_value 0
- 0 3325 8084.12%
- 1 32 77.80%
- 2 80 194.51%
- 3 50 121.57%
- 4 99 240.70%
- 5 52 126.43%
- 6 39 94.82%
- 7 35 85.10%
- 8 401 974.96%
+ 0 2929 7771.29%
+ 1 36 95.52%
+ 2 88 233.48%
+ 3 54 143.27%
+ 4 108 286.55%
+ 5 55 145.93%
+ 6 40 106.13%
+ 7 42 111.44%
+ 8 417 1106.39%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5298.507463 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4556.451613 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1065000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 847500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses 676 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5629.032258 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4489.247312 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 490 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1047000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.275148 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 835000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.275148 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2.634409 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5298.507463 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency
-system.cpu.icache.demand_hits 453 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1065000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses
-system.cpu.icache.demand_misses 201 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 847500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses
+system.cpu.icache.demand_accesses 676 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5629.032258 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
+system.cpu.icache.demand_hits 490 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1047000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.275148 # miss rate for demand accesses
+system.cpu.icache.demand_misses 186 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 835000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.275148 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5298.507463 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 676 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5629.032258 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 453 # number of overall hits
-system.cpu.icache.overall_miss_latency 1065000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses
-system.cpu.icache.overall_misses 201 # number of overall misses
-system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 847500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses
+system.cpu.icache.overall_hits 490 # number of overall hits
+system.cpu.icache.overall_miss_latency 1047000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.275148 # miss rate for overall accesses
+system.cpu.icache.overall_misses 186 # number of overall misses
+system.cpu.icache.overall_mshr_hits 10 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 835000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.275148 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 106.293956 # Cycle average of tags in use
-system.cpu.icache.total_refs 453 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 104.691657 # Cycle average of tags in use
+system.cpu.icache.total_refs 490 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 501 # Number of branches executed
-system.cpu.iew.EXEC:nop 234 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.726477 # Inst execution rate
-system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 333 # Number of stores executed
+system.cpu.idleCycles 998 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 516 # Number of branches executed
+system.cpu.iew.EXEC:nop 242 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.810295 # Inst execution rate
+system.cpu.iew.EXEC:refs 894 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 334 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1652 # num instructions consuming a value
-system.cpu.iew.WB:count 2914 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1725 # num instructions consuming a value
+system.cpu.iew.WB:count 2987 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.794203 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1321 # num instructions producing a value
-system.cpu.iew.WB:rate 0.708485 # insts written-back per cycle
-system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 1370 # num instructions producing a value
+system.cpu.iew.WB:rate 0.792518 # insts written-back per cycle
+system.cpu.iew.WB:sent 3007 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 146 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions
+system.cpu.iew.iewDispLoadInsts 635 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 92 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 367 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 3711 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 560 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 3054 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 225 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.forwLoads 24 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
+system.cpu.iew.lsq.thread.0.squashedLoads 220 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 73 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.580355 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.580355 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued
+system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.633324 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.633324 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 3165 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
- IntAlu 2178 70.83% # Type of FU issued
+ IntAlu 2243 70.87% # Type of FU issued
IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 561 18.24% # Type of FU issued
- MemWrite 335 10.89% # Type of FU issued
+ MemRead 581 18.36% # Type of FU issued
+ MemWrite 340 10.74% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate 0.011058 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 2 5.71% # attempts to use FU when none available
+ IntAlu 1 2.86% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 12 34.29% # attempts to use FU when none available
- MemWrite 21 60.00% # attempts to use FU when none available
+ MemWrite 22 62.86% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 4113
+system.cpu.iq.ISSUE:issued_per_cycle.samples 3769
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 2848 6924.39%
- 1 479 1164.60%
- 2 276 671.04%
- 3 213 517.87%
- 4 158 384.15%
- 5 86 209.09%
- 6 34 82.66%
- 7 13 31.61%
- 8 6 14.59%
+ 0 2469 6550.81%
+ 1 494 1310.69%
+ 2 274 726.98%
+ 3 234 620.85%
+ 4 152 403.29%
+ 5 87 230.83%
+ 6 40 106.13%
+ 7 14 37.15%
+ 8 5 13.27%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.747629 # Inst issue rate
-system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4509.259259 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 1217500 # number of ReadReq miss cycles
+system.cpu.iq.ISSUE:rate 0.839745 # Inst issue rate
+system.cpu.iq.iqInstsAdded 3463 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3165 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 947 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 468 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 25 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 3720 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2720 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 93000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 25 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 68000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 25 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3357.723577 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.723577 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 826000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 580000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 3230.769231 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2230.769231 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 42000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 29000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4509.259259 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3391.143911 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1217500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 919000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 648000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4509.259259 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3391.143911 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1217500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 919000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 270 # number of overall misses
+system.cpu.l2cache.overall_misses 271 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 648000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 158.313436 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 129.636467 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 4113 # number of cpu cycles simulated
+system.cpu.numCycles 3769 # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 2724 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 700 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed
-system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:RenameLookups 4613 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 4068 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2909 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 733 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1141 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 80 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
+system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Jun 21 2007 21:25:27
-M5 started Fri Jun 22 00:04:44 2007
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:13 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2055000 because target called exit()
+Exiting @ tick 1884000 because target called exit()
[system.cpu]
type=AtomicSimpleCPU
-children=workload
+children=tracer workload
clock=500
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
---------- Begin Simulation Statistics ----------
-host_inst_rate 111994 # Simulator instruction rate (inst/s)
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 55017079 # Simulator tick rate (ticks/s)
+host_inst_rate 34280 # Simulator instruction rate (inst/s)
+host_mem_usage 147884 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 17043200 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
All Rights Reserved
-M5 compiled Jun 10 2007 14:06:20
-M5 started Sun Jun 10 14:22:37 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:14 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1288500 because target called exit()
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
---------- Begin Simulation Statistics ----------
-host_inst_rate 51133 # Simulator instruction rate (inst/s)
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 127514531 # Simulator tick rate (ticks/s)
+host_inst_rate 43962 # Simulator instruction rate (inst/s)
+host_mem_usage 153564 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 112042683 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
-sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 6472000 # Number of ticks simulated
+sim_seconds 0.000007 # Number of seconds simulated
+sim_ticks 6615000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 532000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 494000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 1302000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 1209000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 627 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 82 # number of overall misses
+system.cpu.dcache.overall_hits 616 # number of overall hits
+system.cpu.dcache.overall_miss_latency 1302000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 93 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 1209000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 50.044147 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 86.205303 # Cycle average of tags in use
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 324000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 2616000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 132000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 2940000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 2940000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 245 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 109.774164 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 6472000 # number of cpu cycles simulated
+system.cpu.numCycles 6615000 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
All Rights Reserved
-M5 compiled Jun 10 2007 14:06:20
-M5 started Sun Jun 10 14:22:37 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:14 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 6472000 because target called exit()
+Exiting @ tick 6615000 because target called exit()
[system.cpu]
type=AtomicSimpleCPU
-children=workload
+children=tracer workload
clock=500
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
---------- Begin Simulation Statistics ----------
-host_inst_rate 535701 # Simulator instruction rate (inst/s)
-host_mem_usage 148368 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 257653061 # Simulator tick rate (ticks/s)
+host_inst_rate 25511 # Simulator instruction rate (inst/s)
+host_mem_usage 149560 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
+host_tick_rate 12728361 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
All Rights Reserved
-M5 compiled May 15 2007 12:54:05
-M5 started Tue May 15 12:54:07 2007
+M5 compiled Aug 3 2007 04:06:41
+M5 started Fri Aug 3 04:31:09 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
---------- Begin Simulation Statistics ----------
-host_inst_rate 273338 # Simulator instruction rate (inst/s)
-host_mem_usage 153844 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 633390216 # Simulator tick rate (ticks/s)
+host_inst_rate 45085 # Simulator instruction rate (inst/s)
+host_mem_usage 155088 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 101545982 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
-sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13362000 # Number of ticks simulated
+sim_seconds 0.000014 # Number of seconds simulated
+sim_ticks 13544000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 700000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 650000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 896000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 832000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1848000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 2044000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1716000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 1898000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1922 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1848000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 132 # number of overall misses
+system.cpu.dcache.overall_hits 1908 # number of overall hits
+system.cpu.dcache.overall_miss_latency 2044000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 146 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1716000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 1898000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 85.283494 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 85.440937 # Cycle average of tags in use
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 136.309471 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 136.727640 # Cycle average of tags in use
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 600000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 5629000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4763000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 4596000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004619 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 5629000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 5196000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 5629000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 5196000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 433 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 222.872415 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 184.077317 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 13362000 # number of cpu cycles simulated
+system.cpu.numCycles 13544000 # number of cpu cycles simulated
system.cpu.num_insts 5657 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
All Rights Reserved
-M5 compiled May 15 2007 12:54:05
-M5 started Tue May 15 12:54:07 2007
+M5 compiled Aug 3 2007 04:06:41
+M5 started Fri Aug 3 04:31:10 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 13362000 because target called exit()
+Exiting @ tick 13544000 because target called exit()
[system.cpu]
type=AtomicSimpleCPU
-children=workload
+children=tracer workload
clock=500
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
---------- Begin Simulation Statistics ----------
-host_inst_rate 439375 # Simulator instruction rate (inst/s)
-host_mem_usage 149124 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 211870315 # Simulator tick rate (ticks/s)
+host_inst_rate 15625 # Simulator instruction rate (inst/s)
+host_mem_usage 149968 # Number of bytes of host memory used
+host_seconds 0.31 # Real time elapsed on the host
+host_tick_rate 7799892 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
All Rights Reserved
-M5 compiled May 15 2007 13:02:31
-M5 started Tue May 15 17:00:05 2007
+M5 compiled Aug 3 2007 04:11:25
+M5 started Fri Aug 3 04:31:18 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
---------- Begin Simulation Statistics ----------
-host_inst_rate 239687 # Simulator instruction rate (inst/s)
-host_mem_usage 154512 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 542234464 # Simulator tick rate (ticks/s)
+host_inst_rate 36222 # Simulator instruction rate (inst/s)
+host_mem_usage 155556 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 84966253 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000011 # Number of seconds simulated
-sim_ticks 11221000 # Number of ticks simulated
+sim_ticks 11443000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13796.296296 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12796.296296 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 13962.962963 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12962.962963 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 745000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 754000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 691000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 700000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1176000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 1092000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 562 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 1386000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.149773 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 99 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 1287000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.149773 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 99 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 8.195652 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13920.289855 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1921000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 13986.928105 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1116 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 2140000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.120567 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1783000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 1987000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.120567 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13920.289855 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 13986.928105 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1131 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1921000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 138 # number of overall misses
+system.cpu.dcache.overall_hits 1116 # number of overall hits
+system.cpu.dcache.overall_miss_latency 2140000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.120567 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 153 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1783000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 1987000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.120567 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 83.705022 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 83.865949 # Cycle average of tags in use
system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13914.062500 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12914.062500 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 13984.375000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12984.375000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3562000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 3580000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 3306000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 3324000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13914.062500 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 13984.375000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3562000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 3580000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 3306000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 3324000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13914.062500 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 13984.375000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4608 # number of overall hits
-system.cpu.icache.overall_miss_latency 3562000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 3580000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
system.cpu.icache.overall_misses 256 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 3306000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 3324000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 114.172725 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 114.646434 # Cycle average of tags in use
system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 84 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1008000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 84 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 924000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 84 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 5083000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4301000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 3684000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 180000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 5083000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 4692000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 5083000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_hits 3 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 4692000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 391 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 196.304892 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 133.135118 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 11221000 # number of cpu cycles simulated
+system.cpu.numCycles 11443000 # number of cpu cycles simulated
system.cpu.num_insts 4863 # Number of instructions executed
system.cpu.num_refs 1269 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
All Rights Reserved
-M5 compiled May 15 2007 13:02:31
-M5 started Tue May 15 17:00:05 2007
+M5 compiled Aug 3 2007 04:11:25
+M5 started Fri Aug 3 04:31:19 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 11221000 because target called exit()
+Exiting @ tick 11443000 because target called exit()
[system.cpu]
type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload0 workload1
+children=dcache fuPool icache l2cache toL2Bus tracer workload0 workload1
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
smtROBThreshold=100
squashWidth=8
system=system
+tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
[system.cpu.fuPool.FUList0]
type=FUDesc
-children=opList0
+children=opList
count=6
-opList=system.cpu.fuPool.FUList0.opList0
+opList=system.cpu.fuPool.FUList0.opList
-[system.cpu.fuPool.FUList0.opList0]
+[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList4.opList0
+opList=system.cpu.fuPool.FUList4.opList
-[system.cpu.fuPool.FUList4.opList0]
+[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
[system.cpu.fuPool.FUList5]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList5.opList0
+opList=system.cpu.fuPool.FUList5.opList
-[system.cpu.fuPool.FUList5.opList0]
+[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0
+children=opList
count=1
-opList=system.cpu.fuPool.FUList7.opList0
+opList=system.cpu.fuPool.FUList7.opList
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload0]
type=LiveProcess
cmd=hello
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 696 # Number of BTB hits
-global.BPredUnit.BTBLookups 3414 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 125 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 2315 # Number of conditional branches predicted
-global.BPredUnit.lookups 3940 # Number of BP lookups
-global.BPredUnit.usedRAS 525 # Number of times the RAS was used to get a target.
-host_inst_rate 52706 # Simulator instruction rate (inst/s)
-host_mem_usage 154396 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
-host_tick_rate 25698682 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 16 # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 16 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 53 # Number of conflicting stores.
-memdepunit.memDep.conflictingStores 59 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 1934 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 1903 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1082 # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1090 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBLookups 3444 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 120 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1098 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 2319 # Number of conditional branches predicted
+global.BPredUnit.lookups 3987 # Number of BP lookups
+global.BPredUnit.usedRAS 539 # Number of times the RAS was used to get a target.
+host_inst_rate 43485 # Simulator instruction rate (inst/s)
+host_mem_usage 155152 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
+host_tick_rate 19795862 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 48 # Number of conflicting stores.
+memdepunit.memDep.conflictingStores 52 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 1908 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 1873 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1098 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1086 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 11247 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated
-sim_ticks 5491500 # Number of ticks simulated
+sim_ticks 5126000 # Number of ticks simulated
system.cpu.commit.COM:branches 1724 # Number of branches committed
system.cpu.commit.COM:branches_0 862 # Number of branches committed
system.cpu.commit.COM:branches_1 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 168 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 10926
+system.cpu.commit.COM:committed_per_cycle.samples 10208
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 6353 5814.57%
- 1 2078 1901.89%
- 2 996 911.59%
- 3 472 432.00%
- 4 296 270.91%
- 5 241 220.57%
- 6 192 175.73%
- 7 130 118.98%
- 8 168 153.76%
+ 0 5629 5514.30%
+ 1 2071 2028.80%
+ 2 984 963.95%
+ 3 471 461.40%
+ 4 357 349.73%
+ 5 228 223.35%
+ 6 179 175.35%
+ 7 125 122.45%
+ 8 164 160.66%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 885 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 852 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 7777 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 7556 # The number of squashed insts skipped by commit
system.cpu.committedInsts_0 5623 # Number of Instructions Simulated
system.cpu.committedInsts_1 5624 # Number of Instructions Simulated
system.cpu.committedInsts_total 11247 # Number of Instructions Simulated
-system.cpu.cpi_0 1.952872 # CPI: Cycles Per Instruction
-system.cpu.cpi_1 1.952525 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.976349 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 2981 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses_0 2981 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency_0 7040.892193 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6979.591837 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2712 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits_0 2712 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1894000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency_0 1894000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate_0 0.090238 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 269 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses_0 269 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits_0 73 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1368000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency_0 1368000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.065750 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 196 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses_0 196 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency_0 5306.613226 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 5852.739726 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 1125 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits_0 1125 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2648000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency_0 2648000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate_0 0.307266 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 499 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses_0 499 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 353 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits_0 353 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 854500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency_0 854500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses
+system.cpu.cpi_0 1.822870 # CPI: Cycles Per Instruction
+system.cpu.cpi_1 1.822546 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.911354 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 2898 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses_0 2898 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency_0 10388.059701 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7328.358209 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2697 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits_0 2697 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2088000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency_0 2088000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate_0 0.069358 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 201 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses_0 201 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 74 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits_0 74 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1473000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency_0 1473000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.069358 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 201 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses_0 201 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 1265 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses_0 1265 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency_0 16353.448276 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 5663.793103 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 1091 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits_0 1091 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 2845500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency_0 2845500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate_0 0.137549 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 174 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses_0 174 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 359 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits_0 359 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 985500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency_0 985500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.137549 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.219298 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 10.997118 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 4605 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses_0 4605 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 4163 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses_0 4163 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_0 5914.062500 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_0 13156 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_0 6498.538012 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_0 6556 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 3837 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits_0 3837 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 3788 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits_0 3788 # number of demand (read+write) hits
system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4542000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_0 4542000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 4933500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_0 4933500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_0 0.166775 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_0 0.090079 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_misses 768 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses_0 768 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 375 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses_0 375 # number of demand (read+write) misses
system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 426 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_0 426 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits 433 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_0 433 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 2222500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_0 2222500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 2458500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_0 2458500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_0 0.074267 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_0 0.090079 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 342 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses_0 342 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 375 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses_0 375 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 4605 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses_0 4605 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 4163 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses_0 4163 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_0 5914.062500 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_0 13156 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_0 6498.538012 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_0 6556 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 3837 # number of overall hits
-system.cpu.dcache.overall_hits_0 3837 # number of overall hits
+system.cpu.dcache.overall_hits 3788 # number of overall hits
+system.cpu.dcache.overall_hits_0 3788 # number of overall hits
system.cpu.dcache.overall_hits_1 0 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4542000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_0 4542000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 4933500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_0 4933500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_0 0.166775 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_0 0.090079 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_misses 768 # number of overall misses
-system.cpu.dcache.overall_misses_0 768 # number of overall misses
+system.cpu.dcache.overall_misses 375 # number of overall misses
+system.cpu.dcache.overall_misses_0 375 # number of overall misses
system.cpu.dcache.overall_misses_1 0 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 426 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_0 426 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits 433 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_0 433 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 2222500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_0 2222500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 2458500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_0 2458500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_0 0.074267 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_0 0.090079 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 342 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses_0 342 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 375 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses_0 375 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.replacements_0 0 # number of replacements
system.cpu.dcache.replacements_1 0 # number of replacements
-system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 221.287284 # Cycle average of tags in use
-system.cpu.dcache.total_refs 3837 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 222.253048 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3816 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks_0 0 # number of writebacks
system.cpu.dcache.writebacks_1 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 1876 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 246 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 345 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 21769 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 14522 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 3673 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1511 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 346 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 145 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 3940 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 3009 # Number of cache lines fetched
-system.cpu.fetch.Cycles 6972 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 537 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 23897 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 1189 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.358802 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 3009 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1221 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.176213 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:BlockedCycles 1825 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 258 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 356 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 21887 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 13153 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 3652 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1444 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 187 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 3987 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 2956 # Number of cache lines fetched
+system.cpu.fetch.Cycles 6947 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 423 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 24040 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.388976 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 2956 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1235 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.345366 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 10981
+system.cpu.fetch.rateDist.samples 10250
system.cpu.fetch.rateDist.min_value 0
- 0 7019 6391.95%
- 1 293 266.82%
- 2 225 204.90%
- 3 260 236.77%
- 4 345 314.18%
- 5 288 262.27%
- 6 304 276.84%
- 7 246 224.02%
- 8 2001 1822.24%
+ 0 6260 6107.32%
+ 1 296 288.78%
+ 2 229 223.41%
+ 3 268 261.46%
+ 4 338 329.76%
+ 5 294 286.83%
+ 6 303 295.61%
+ 7 254 247.80%
+ 8 2008 1959.02%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 3009 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses_0 3009 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency_0 5911.144578 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5119.774920 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 2345 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits_0 2345 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3925000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency_0 3925000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate_0 0.220671 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 664 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses_0 664 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 42 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits_0 42 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 3184500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency_0 3184500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate_0 0.206713 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 622 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses_0 622 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 2906 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses_0 2906 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency_0 6488.691438 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5218.093700 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 2287 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits_0 2287 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 4016500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency_0 4016500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate_0 0.213008 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 619 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses_0 619 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits_0 50 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency_0 3230000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate_0 0.213008 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.770096 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.694669 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 3009 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses_0 3009 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 2906 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses_0 2906 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency_0 5911.144578 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency_0 6488.691438 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency_0 5119.774920 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency_0 5218.093700 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 2345 # number of demand (read+write) hits
-system.cpu.icache.demand_hits_0 2345 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 2287 # number of demand (read+write) hits
+system.cpu.icache.demand_hits_0 2287 # number of demand (read+write) hits
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3925000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency_0 3925000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 4016500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency_0 4016500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_0 0.220671 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_0 0.213008 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_misses 664 # number of demand (read+write) misses
-system.cpu.icache.demand_misses_0 664 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 619 # number of demand (read+write) misses
+system.cpu.icache.demand_misses_0 619 # number of demand (read+write) misses
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 42 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits_0 42 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits 50 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits_0 50 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 3184500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency_0 3184500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 3230000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency_0 3230000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_0 0.206713 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_0 0.213008 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 622 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses_0 622 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 3009 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses_0 3009 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 2906 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses_0 2906 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency_0 5911.144578 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency_0 6488.691438 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency_0 5119.774920 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency_0 5218.093700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 2345 # number of overall hits
-system.cpu.icache.overall_hits_0 2345 # number of overall hits
+system.cpu.icache.overall_hits 2287 # number of overall hits
+system.cpu.icache.overall_hits_0 2287 # number of overall hits
system.cpu.icache.overall_hits_1 0 # number of overall hits
-system.cpu.icache.overall_miss_latency 3925000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency_0 3925000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 4016500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency_0 4016500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_0 0.220671 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_0 0.213008 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_misses 664 # number of overall misses
-system.cpu.icache.overall_misses_0 664 # number of overall misses
+system.cpu.icache.overall_misses 619 # number of overall misses
+system.cpu.icache.overall_misses_0 619 # number of overall misses
system.cpu.icache.overall_misses_1 0 # number of overall misses
-system.cpu.icache.overall_mshr_hits 42 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits_0 42 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits 50 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits_0 50 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 3184500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency_0 3184500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 3230000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency_0 3230000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_0 0.206713 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_0 0.213008 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 622 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses_0 622 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 9 # number of replacements
system.cpu.icache.replacements_0 9 # number of replacements
system.cpu.icache.replacements_1 0 # number of replacements
-system.cpu.icache.sampled_refs 622 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 323.196356 # Cycle average of tags in use
-system.cpu.icache.total_refs 2345 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 320.555850 # Cycle average of tags in use
+system.cpu.icache.total_refs 2287 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.writebacks_0 0 # number of writebacks
system.cpu.icache.writebacks_1 0 # number of writebacks
system.cpu.idleCycles 2997 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 2377 # Number of branches executed
-system.cpu.iew.EXEC:branches_0 1192 # Number of branches executed
-system.cpu.iew.EXEC:branches_1 1185 # Number of branches executed
-system.cpu.iew.EXEC:nop 72 # number of nop insts executed
+system.cpu.iew.EXEC:branches 2346 # Number of branches executed
+system.cpu.iew.EXEC:branches_0 1165 # Number of branches executed
+system.cpu.iew.EXEC:branches_1 1181 # Number of branches executed
+system.cpu.iew.EXEC:nop 71 # number of nop insts executed
system.cpu.iew.EXEC:nop_0 37 # number of nop insts executed
-system.cpu.iew.EXEC:nop_1 35 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.419725 # Inst execution rate
-system.cpu.iew.EXEC:refs 5002 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_0 2507 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_1 2495 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1874 # Number of stores executed
-system.cpu.iew.EXEC:stores_0 933 # Number of stores executed
-system.cpu.iew.EXEC:stores_1 941 # Number of stores executed
+system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.504390 # Inst execution rate
+system.cpu.iew.EXEC:refs 4985 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_0 2501 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_1 2484 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1875 # Number of stores executed
+system.cpu.iew.EXEC:stores_0 943 # Number of stores executed
+system.cpu.iew.EXEC:stores_1 932 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 10260 # num instructions consuming a value
-system.cpu.iew.WB:consumers_0 5135 # num instructions consuming a value
-system.cpu.iew.WB:consumers_1 5125 # num instructions consuming a value
-system.cpu.iew.WB:count 14994 # cumulative count of insts written-back
-system.cpu.iew.WB:count_0 7526 # cumulative count of insts written-back
-system.cpu.iew.WB:count_1 7468 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 1.530607 # average fanout of values written-back
-system.cpu.iew.WB:fanout_0 0.763778 # average fanout of values written-back
-system.cpu.iew.WB:fanout_1 0.766829 # average fanout of values written-back
+system.cpu.iew.WB:consumers 10076 # num instructions consuming a value
+system.cpu.iew.WB:consumers_0 5067 # num instructions consuming a value
+system.cpu.iew.WB:consumers_1 5009 # num instructions consuming a value
+system.cpu.iew.WB:count 14858 # cumulative count of insts written-back
+system.cpu.iew.WB:count_0 7442 # cumulative count of insts written-back
+system.cpu.iew.WB:count_1 7416 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 1.533770 # average fanout of values written-back
+system.cpu.iew.WB:fanout_0 0.764555 # average fanout of values written-back
+system.cpu.iew.WB:fanout_1 0.769215 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 7852 # num instructions producing a value
-system.cpu.iew.WB:producers_0 3922 # num instructions producing a value
-system.cpu.iew.WB:producers_1 3930 # num instructions producing a value
-system.cpu.iew.WB:rate 1.365449 # insts written-back per cycle
-system.cpu.iew.WB:rate_0 0.685366 # insts written-back per cycle
-system.cpu.iew.WB:rate_1 0.680084 # insts written-back per cycle
-system.cpu.iew.WB:sent 15132 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_0 7582 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_1 7550 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 958 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 6 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 3837 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 7727 # num instructions producing a value
+system.cpu.iew.WB:producers_0 3874 # num instructions producing a value
+system.cpu.iew.WB:producers_1 3853 # num instructions producing a value
+system.cpu.iew.WB:rate 1.449561 # insts written-back per cycle
+system.cpu.iew.WB:rate_0 0.726049 # insts written-back per cycle
+system.cpu.iew.WB:rate_1 0.723512 # insts written-back per cycle
+system.cpu.iew.WB:sent 14990 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_0 7512 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_1 7478 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 976 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 3781 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 445 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 2172 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 19086 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 3128 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_0 1574 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_1 1554 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 852 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 15590 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 481 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 2184 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 18854 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 3110 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_0 1558 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_1 1552 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 865 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 15420 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1511 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 1444 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 43 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 37 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 65 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 955 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 270 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 929 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 286 # Number of stores squashed
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.1.forwLoads 42 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.1.forwLoads 44 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.memOrderViolation 58 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.1.memOrderViolation 65 # Number of memory ordering violations
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.1.squashedLoads 924 # Number of loads squashed
-system.cpu.iew.lsq.thread.1.squashedStores 278 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 122 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 767 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 191 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc_0 0.512066 # IPC: Instructions Per Cycle
-system.cpu.ipc_1 0.512157 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.024224 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 8235 # Type of FU issued
+system.cpu.iew.lsq.thread.1.squashedLoads 894 # Number of loads squashed
+system.cpu.iew.lsq.thread.1.squashedStores 274 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 130 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 783 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 193 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc_0 0.548585 # IPC: Instructions Per Cycle
+system.cpu.ipc_1 0.548683 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.097268 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 8178 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 5567 67.60% # Type of FU issued
+ IntAlu 5509 67.36% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1702 20.67% # Type of FU issued
- MemWrite 961 11.67% # Type of FU issued
+ MemRead 1692 20.69% # Type of FU issued
+ MemWrite 972 11.89% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:FU_type_1 8207 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1 8107 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 5547 67.59% # Type of FU issued
+ IntAlu 5452 67.25% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1690 20.59% # Type of FU issued
- MemWrite 965 11.76% # Type of FU issued
+ MemRead 1681 20.74% # Type of FU issued
+ MemWrite 969 11.95% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.end_dist
-system.cpu.iq.ISSUE:FU_type 16442 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type 16285 # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
No_OpClass 4 0.02% # Type of FU issued
- IntAlu 11114 67.60% # Type of FU issued
+ IntAlu 10961 67.31% # Type of FU issued
IntMult 2 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 4 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 3392 20.63% # Type of FU issued
- MemWrite 1926 11.71% # Type of FU issued
+ MemRead 3373 20.71% # Type of FU issued
+ MemWrite 1941 11.92% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 189 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_0 98 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_1 91 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011495 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_0 0.005960 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_1 0.005535 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_0 92 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_1 88 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011053 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_0 0.005649 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_1 0.005404 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 14 7.41% # attempts to use FU when none available
+ IntAlu 7 3.89% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 107 56.61% # attempts to use FU when none available
- MemWrite 68 35.98% # attempts to use FU when none available
+ MemRead 112 62.22% # attempts to use FU when none available
+ MemWrite 61 33.89% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 10981
+system.cpu.iq.ISSUE:issued_per_cycle.samples 10250
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 4775 4348.42%
- 1 1817 1654.68%
- 2 1638 1491.67%
- 3 1107 1008.10%
- 4 745 678.44%
- 5 490 446.23%
- 6 287 261.36%
- 7 100 91.07%
- 8 22 20.03%
+ 0 4091 3991.22%
+ 1 1777 1733.66%
+ 2 1632 1592.20%
+ 3 1101 1074.15%
+ 4 778 759.02%
+ 5 523 510.24%
+ 6 249 242.93%
+ 7 72 70.24%
+ 8 27 26.34%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.497314 # Inst issue rate
-system.cpu.iq.iqInstsAdded 18972 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 16442 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 1.588780 # Inst issue rate
+system.cpu.iq.iqInstsAdded 18741 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 16285 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 6918 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6728 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 4274 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 962 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses_0 962 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency_0 5208.636837 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2724.765869 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 5005500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency_0 5005500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate_0 0.998960 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 961 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses_0 961 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 2618500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2618500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998960 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 961 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses_0 961 # number of ReadReq MSHR misses
+system.cpu.iq.iqSquashedOperandsExamined 4160 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency_0 3893.835616 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2893.835616 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 568500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency_0 568500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 422500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 422500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses_0 820 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency_0 3880.368098 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2880.368098 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits_0 5 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 3162500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency_0 3162500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate_0 0.993902 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 815 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses_0 815 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 2347500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2347500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.993902 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 815 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses_0 815 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 3392.857143 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2392.857143 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 95000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency_0 95000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 67000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 67000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.001041 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.006353 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 962 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_0 962 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_0 966 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency_0 5208.636837 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency_0 3882.414152 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2724.765869 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2882.414152 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits_0 5 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 5005500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency_0 5005500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 3731000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency_0 3731000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_0 0.998960 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_0 0.994824 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
system.cpu.l2cache.demand_misses 961 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses_0 961 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2618500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency_0 2618500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 2770000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency_0 2770000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_0 0.998960 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_0 0.994824 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 961 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses_0 961 # number of demand (read+write) MSHR misses
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 962 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_0 962 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_0 966 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency_0 5208.636837 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency_0 3882.414152 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2724.765869 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2882.414152 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_hits_0 1 # number of overall hits
+system.cpu.l2cache.overall_hits 5 # number of overall hits
+system.cpu.l2cache.overall_hits_0 5 # number of overall hits
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 5005500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency_0 5005500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 3731000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency_0 3731000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_0 0.998960 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_0 0.994824 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
system.cpu.l2cache.overall_misses 961 # number of overall misses
system.cpu.l2cache.overall_misses_0 961 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2618500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency_0 2618500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 2770000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency_0 2770000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_0 0.998960 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_0 0.994824 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 961 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses_0 961 # number of overall MSHR misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.replacements_0 0 # number of replacements
system.cpu.l2cache.replacements_1 0 # number of replacements
-system.cpu.l2cache.sampled_refs 961 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 787 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 545.318204 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 430.884580 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.writebacks_0 0 # number of writebacks
system.cpu.l2cache.writebacks_1 0 # number of writebacks
-system.cpu.numCycles 10981 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 612 # Number of cycles rename is blocking
+system.cpu.numCycles 10250 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 14828 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 692 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 26356 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 20731 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 15606 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 3494 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1511 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 761 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 7504 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 521 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IdleCycles 13468 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 717 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 26379 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 20752 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 15596 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 3515 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1444 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 772 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 7494 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 497 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2159 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 2091 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
All Rights Reserved
-M5 compiled Jun 21 2007 21:25:27
-M5 started Fri Jun 22 00:04:51 2007
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:15 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 5491500 because target called exit()
+Exiting @ tick 5126000 because target called exit()
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu0.tracer
width=1
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu0.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.port[2]
-[system.cpu0.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu0.dtb]
type=AlphaDTB
size=64
[system.cpu0.icache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=1
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu0.icache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
-[system.cpu0.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu0.itb]
type=AlphaITB
size=48
+[system.cpu0.tracer]
+type=ExeTracer
+
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
clock=500
cpu_id=1
defer_registration=false
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu1.tracer
width=1
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu1.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.port[4]
-[system.cpu1.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu1.dtb]
type=AlphaDTB
size=64
[system.cpu1.icache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=1
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu1.icache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
-[system.cpu1.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu1.itb]
type=AlphaITB
size=48
+[system.cpu1.tracer]
+type=ExeTracer
+
[system.disk0]
type=IdeDisk
children=image
[system.l2c]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=8
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=4194304
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
pio_latency=1000
platform=system.tsunami
system=system
-time=2009 1 1 0 0 0 3 1
+time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]
---------- Begin Simulation Statistics ----------
-host_inst_rate 1418499 # Simulator instruction rate (inst/s)
-host_seconds 44.50 # Real time elapsed on the host
-host_tick_rate 42028043491 # Simulator tick rate (ticks/s)
+host_inst_rate 1258571 # Simulator instruction rate (inst/s)
+host_mem_usage 256444 # Number of bytes of host memory used
+host_seconds 50.16 # Real time elapsed on the host
+host_tick_rate 37289409683 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63125943 # Number of instructions simulated
sim_seconds 1.870335 # Number of seconds simulated
sim_ticks 1870335101500 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits 7464198 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate 0.185482 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1699743 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 5646722 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 286674 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses
+system.cpu0.dcache.ReadReq_accesses 8975658 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_hits 7292076 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_rate 0.187572 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 1683582 # number of ReadReq misses
+system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_hits 159819 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_rate 0.146827 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses 27504 # number of StoreCondReq misses
+system.cpu0.dcache.WriteReq_accesses 5746073 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_hits 5372266 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 373807 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 6.625567 # Average number of references to valid blocks.
system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses 14721731 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 13110920 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits 12664342 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.131574 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 1986417 # number of demand (read+write) misses
+system.cpu0.dcache.demand_miss_rate 0.139752 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 2057389 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses 14721731 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 13110920 # number of overall hits
+system.cpu0.dcache.overall_hits 12664342 # number of overall hits
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.131574 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 1986417 # number of overall misses
+system.cpu0.dcache.overall_miss_rate 0.139752 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 2057389 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu0.dcache.protocol.read_invalid 1699743 # read misses to invalid blocks
-system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_read_owned 121 # read snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu0.dcache.protocol.write_invalid 282338 # write misses to invalid blocks
-system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks
-system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks
system.cpu0.dcache.replacements 1978980 # number of replacements
system.cpu0.dcache.sampled_refs 1979492 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13115256 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 0 # number of writebacks
+system.cpu0.dcache.writebacks 396796 # number of writebacks
system.cpu0.dtb.accesses 698037 # DTB accesses
system.cpu0.dtb.acv 251 # DTB access violations
system.cpu0.dtb.hits 15082969 # DTB hits
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks
-system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu0.icache.protocol.snoop_read_exclusive 25832 # read snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
-system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
-system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks
-system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
-system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks
-system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks
-system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks
-system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks
system.cpu0.icache.replacements 884276 # number of replacements
system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.numCycles 57193784 # number of cpu cycles simulated
system.cpu0.num_insts 57190172 # Number of instructions executed
system.cpu0.num_refs 15322419 # Number of memory references
-system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses
+system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses
+system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses
+system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks.
system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses
+system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 1847506 # number of overall hits
+system.cpu1.dcache.overall_hits 1812115 # number of overall hits
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 69527 # number of overall misses
+system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 72155 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks
-system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_read_shared 61772 # read snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks
-system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks
-system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks
system.cpu1.dcache.replacements 62341 # number of replacements
system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use
system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 0 # number of writebacks
+system.cpu1.dcache.writebacks 30850 # number of writebacks
system.cpu1.dtb.accesses 323622 # DTB accesses
system.cpu1.dtb.acv 116 # DTB access violations
system.cpu1.dtb.hits 1914885 # DTB hits
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks
-system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu1.icache.protocol.snoop_read_exclusive 17317 # read snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
-system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
-system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks
-system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
-system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks
-system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks
-system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks
-system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks
system.cpu1.icache.replacements 103097 # number of replacements
system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits 181108 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate 0.408619 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses
system.l2c.ReadReq_accesses 2724166 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 1782863 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.345538 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 941303 # number of ReadReq misses
-system.l2c.Writeback_accesses 427634 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 427634 # number of Writeback hits
+system.l2c.ReadReq_hits 1625506 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate 0.403301 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 1098660 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses 125013 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 125013 # number of UpgradeReq misses
+system.l2c.Writeback_accesses 427646 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.l2c.Writeback_misses 427646 # number of Writeback misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 2.242879 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.720013 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2724166 # number of demand (read+write) accesses
+system.l2c.demand_accesses 3030412 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.demand_hits 1782863 # number of demand (read+write) hits
+system.l2c.demand_hits 1625506 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.345538 # miss rate for demand accesses
-system.l2c.demand_misses 941303 # number of demand (read+write) misses
+system.l2c.demand_miss_rate 0.463602 # miss rate for demand accesses
+system.l2c.demand_misses 1404906 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3151800 # number of overall (read+write) accesses
+system.l2c.overall_accesses 3030412 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 2210497 # number of overall hits
+system.l2c.overall_hits 1625506 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.298656 # miss rate for overall accesses
-system.l2c.overall_misses 941303 # number of overall misses
+system.l2c.overall_miss_rate 0.463602 # miss rate for overall accesses
+system.l2c.overall_misses 1404906 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 1000779 # number of replacements
-system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks.
+system.l2c.replacements 947869 # number of replacements
+system.l2c.sampled_refs 966791 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 65517.575356 # Cycle average of tags in use
-system.l2c.total_refs 2391266 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit.
+system.l2c.tagsinuse 15587.342424 # Cycle average of tags in use
+system.l2c.total_refs 1662893 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-Listening for system connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
-0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
+Listening for system connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
+0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: 97861500: Trying to launch CPU number 1!
All Rights Reserved
-M5 compiled Jun 10 2007 14:10:03
-M5 started Mon Jun 11 01:04:58 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+M5 compiled Aug 3 2007 04:02:11
+M5 started Fri Aug 3 04:22:43 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-Exiting @ tick 1870335097000 because m5_exit instruction encountered
+Exiting @ tick 1870335101500 because m5_exit instruction encountered
[system.cpu]
type=AtomicSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=system
+tracer=system.cpu.tracer
width=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.port[2]
-[system.cpu.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=1
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu.icache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu.icache_port
mem_side=system.toL2Bus.port[1]
-[system.cpu.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu.itb]
type=AlphaITB
size=48
+[system.cpu.tracer]
+type=ExeTracer
+
[system.disk0]
type=IdeDisk
children=image
[system.l2c]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=8
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=4194304
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
pio_latency=1000
platform=system.tsunami
system=system
-time=2009 1 1 0 0 0 3 1
+time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]
---------- Begin Simulation Statistics ----------
-host_inst_rate 1403977 # Simulator instruction rate (inst/s)
-host_seconds 42.74 # Real time elapsed on the host
-host_tick_rate 42777462102 # Simulator tick rate (ticks/s)
+host_inst_rate 1294756 # Simulator instruction rate (inst/s)
+host_mem_usage 255900 # Number of bytes of host memory used
+host_seconds 46.35 # Real time elapsed on the host
+host_tick_rate 39449403667 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60007317 # Number of instructions simulated
sim_seconds 1.828355 # Number of seconds simulated
-sim_ticks 1828355486000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits 7984498 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1738835 # number of ReadReq misses
-system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses
+sim_ticks 1828355476000 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits 7801377 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1721677 # number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses
+system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 6.866566 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 6.866558 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 14029591 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 13552149 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2043189 # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2121094 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 14029591 # number of overall hits
+system.cpu.dcache.overall_hits 13552149 # number of overall hits
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2043189 # number of overall misses
+system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2121094 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu.dcache.protocol.read_invalid 1738835 # read misses to invalid blocks
-system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks
-system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks
-system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks
-system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks
-system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
-system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks
-system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks
-system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks
-system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks
-system.cpu.dcache.replacements 2042664 # number of replacements
-system.cpu.dcache.sampled_refs 2043176 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 2042666 # number of replacements
+system.cpu.dcache.sampled_refs 2043178 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14029603 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 14029601 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dcache.writebacks 428885 # number of writebacks
system.cpu.dtb.accesses 1020787 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
system.cpu.dtb.hits 16053818 # DTB hits
system.cpu.dtb.write_hits 6349968 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 59087260 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses 920057 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 64.229332 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 59087260 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses
-system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 920057 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 59087263 # number of overall hits
+system.cpu.icache.overall_hits 59087260 # number of overall hits
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses
-system.cpu.icache.overall_misses 920054 # number of overall misses
+system.cpu.icache.overall_misses 920057 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks
-system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
-system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
-system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks
-system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks
-system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks
-system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks
-system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks
-system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks
-system.cpu.icache.replacements 919427 # number of replacements
-system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 919430 # number of replacements
+system.cpu.icache.sampled_refs 919942 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use
-system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 59087260 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0.983588 # Percentage of idle cycles
system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 1828355278500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 1811087547500 99.06% 99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks 1828355268500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1811087537500 99.06% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 1800056182000 98.45% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1800056172000 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses
-system.l2c.ReadReq_accesses 2658872 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 1717828 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 941044 # number of ReadReq misses
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses
+system.l2c.ReadReq_accesses 2658877 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits 1558398 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate 0.413889 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 1100479 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses
system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 428885 # number of Writeback hits
+system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.l2c.Writeback_misses 428885 # number of Writeback misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 2.205901 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.644070 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2658872 # number of demand (read+write) accesses
+system.l2c.demand_accesses 2963219 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.demand_hits 1717828 # number of demand (read+write) hits
+system.l2c.demand_hits 1558398 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses
-system.l2c.demand_misses 941044 # number of demand (read+write) misses
+system.l2c.demand_miss_rate 0.474086 # miss rate for demand accesses
+system.l2c.demand_misses 1404821 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3087757 # number of overall (read+write) accesses
+system.l2c.overall_accesses 2963219 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 2146713 # number of overall hits
+system.l2c.overall_hits 1558398 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses
-system.l2c.overall_misses 941044 # number of overall misses
+system.l2c.overall_miss_rate 0.474086 # miss rate for overall accesses
+system.l2c.overall_misses 1404821 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 992432 # number of replacements
-system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks.
+system.l2c.replacements 947436 # number of replacements
+system.l2c.sampled_refs 965232 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use
-system.l2c.total_refs 2333446 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
+system.l2c.tagsinuse 15309.548937 # Cycle average of tags in use
+system.l2c.total_refs 1586909 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 789998500 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-Listening for system connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+Listening for system connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
All Rights Reserved
-M5 compiled Jun 10 2007 14:10:03
-M5 started Mon Jun 11 00:55:45 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+M5 compiled Aug 3 2007 04:02:11
+M5 started Fri Aug 3 04:21:55 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-Exiting @ tick 1828355481500 because m5_exit instruction encountered
+Exiting @ tick 1828355476000 because m5_exit instruction encountered
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
profile=0
progress_interval=0
system=system
+tracer=system.cpu0.tracer
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu0.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.port[2]
-[system.cpu0.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu0.dtb]
type=AlphaDTB
size=64
[system.cpu0.icache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=1
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu0.icache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
-[system.cpu0.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu0.itb]
type=AlphaITB
size=48
+[system.cpu0.tracer]
+type=ExeTracer
+
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
clock=500
cpu_id=1
defer_registration=false
profile=0
progress_interval=0
system=system
+tracer=system.cpu1.tracer
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu1.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.port[4]
-[system.cpu1.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu1.dtb]
type=AlphaDTB
size=64
[system.cpu1.icache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=1
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu1.icache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
-[system.cpu1.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu1.itb]
type=AlphaITB
size=48
+[system.cpu1.tracer]
+type=ExeTracer
+
[system.disk0]
type=IdeDisk
children=image
[system.l2c]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=8
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=4194304
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
pio_latency=1000
platform=system.tsunami
system=system
-time=2009 1 1 0 0 0 3 1
+time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]
---------- Begin Simulation Statistics ----------
-host_inst_rate 62524 # Simulator instruction rate (inst/s)
-host_seconds 1011.60 # Real time elapsed on the host
-host_tick_rate 1928760125 # Simulator tick rate (ticks/s)
+host_inst_rate 608366 # Simulator instruction rate (inst/s)
+host_mem_usage 227884 # Number of bytes of host memory used
+host_seconds 106.58 # Real time elapsed on the host
+host_tick_rate 18308931831 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 63248814 # Number of instructions simulated
-sim_seconds 1.951129 # Number of seconds simulated
-sim_ticks 1951129131000 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 9299202 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 13073.177688 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12073.152824 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_hits 7589849 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 22346675500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.183817 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1709353 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 20637280000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.183817 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 1709353 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable 6873 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu0.dcache.ReadResp_mshr_uncacheable_latency 841915000 # number of ReadResp MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_accesses 6016348 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 12644.438594 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 11630.972878 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 5727689 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 3649931000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.047979 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 288659 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 3357385000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.047979 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 288659 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable 9698 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu0.dcache.WriteResp_mshr_uncacheable_latency 1186164500 # number of WriteResp MSHR uncacheable cycles
+sim_insts 64839479 # Number of instructions simulated
+sim_seconds 1.951367 # Number of seconds simulated
+sim_ticks 1951367346000 # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses 150248 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 10860.561606 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9860.561606 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits 136751 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 146585000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate 0.089831 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses 13497 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 133088000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.089831 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses 13497 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses 7920707 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 13239.029006 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12239.003253 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_hits 6328668 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 21077050500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.200997 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 1592039 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency 19484970500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.200997 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses 1592039 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 846944000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses 149727 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 12266.165876 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 11266.165876 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits 126963 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 279227000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate 0.152037 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses 22764 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 256463000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.152037 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses 22764 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses 4824283 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 13877.297001 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 12877.297001 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_hits 4508382 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 4383852000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.065481 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 315901 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency 4067951000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.065481 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 315901 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1297859000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 6.687909 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 6.121232 # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 15315550 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 13011.236419 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 13317538 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 25996606500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.130456 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 1998012 # number of demand (read+write) misses
+system.cpu0.dcache.demand_accesses 12744990 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 13344.708167 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 12344.686678 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 10837050 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 25460902500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.149701 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 1907940 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 23994665000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.130456 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 1998012 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_miss_latency 23552921500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.149701 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 1907940 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 15315550 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 13011.236419 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 13317538 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 25996606500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.130456 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 1998012 # number of overall misses
+system.cpu0.dcache.overall_accesses 12744990 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 13344.708167 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 12344.686678 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits 10837050 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 25460902500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.149701 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 1907940 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 23994665000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.130456 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 1998012 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 16571 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_miss_latency 23552921500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.149701 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 1907940 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 2144803000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu0.dcache.protocol.read_invalid 1709421 # read misses to invalid blocks
-system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu0.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_read_exclusive 908 # read snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_read_modified 3762 # read snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_read_owned 72 # read snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_read_shared 2297 # read snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_readex_exclusive 235 # readEx snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_readex_modified 207 # readEx snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_readex_owned 15 # readEx snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_readex_shared 7 # readEx snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_upgrade_owned 1074 # upgrade snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_upgrade_shared 726 # upgradee snoops on shared blocks
-system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu0.dcache.protocol.write_invalid 284810 # write misses to invalid blocks
-system.cpu0.dcache.protocol.write_owned 2533 # write misses to owned blocks
-system.cpu0.dcache.protocol.write_shared 1354 # write misses to shared blocks
-system.cpu0.dcache.replacements 1991354 # number of replacements
-system.cpu0.dcache.sampled_refs 1991866 # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements 1829212 # number of replacements
+system.cpu0.dcache.sampled_refs 1829724 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 503.775443 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13321418 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 57953000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 401606 # number of writebacks
-system.cpu0.dtb.accesses 719860 # DTB accesses
-system.cpu0.dtb.acv 289 # DTB access violations
-system.cpu0.dtb.hits 15299767 # DTB hits
-system.cpu0.dtb.misses 8485 # DTB misses
-system.cpu0.dtb.read_accesses 524201 # DTB read accesses
-system.cpu0.dtb.read_acv 174 # DTB read access violations
-system.cpu0.dtb.read_hits 9282693 # DTB read hits
-system.cpu0.dtb.read_misses 7687 # DTB read misses
-system.cpu0.dtb.write_accesses 195659 # DTB write accesses
-system.cpu0.dtb.write_acv 115 # DTB write access violations
-system.cpu0.dtb.write_hits 6017074 # DTB write hits
-system.cpu0.dtb.write_misses 798 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 57872551 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 12029.752588 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11029.000057 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 56957639 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 11006165000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.015809 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 914912 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 10090564500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.015809 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 914912 # number of ReadReq MSHR misses
+system.cpu0.dcache.tagsinuse 497.900810 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 11200165 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 58293000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 322933 # number of writebacks
+system.cpu0.dtb.accesses 725071 # DTB accesses
+system.cpu0.dtb.acv 305 # DTB access violations
+system.cpu0.dtb.hits 13035385 # DTB hits
+system.cpu0.dtb.misses 8682 # DTB misses
+system.cpu0.dtb.read_accesses 527638 # DTB read accesses
+system.cpu0.dtb.read_acv 184 # DTB read access violations
+system.cpu0.dtb.read_hits 8058540 # DTB read hits
+system.cpu0.dtb.read_misses 7858 # DTB read misses
+system.cpu0.dtb.write_accesses 197433 # DTB write accesses
+system.cpu0.dtb.write_acv 121 # DTB write access violations
+system.cpu0.dtb.write_hits 4976845 # DTB write hits
+system.cpu0.dtb.write_misses 824 # DTB write misses
+system.cpu0.icache.ReadReq_accesses 51081135 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 12048.344860 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11047.036239 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits 50399501 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 8212561500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate 0.013344 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 681634 # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency 7530035500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate 0.013344 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses 681634 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 62.632934 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 73.953888 # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 57872551 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 12029.752588 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 56957639 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 11006165000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.015809 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 914912 # number of demand (read+write) misses
+system.cpu0.icache.demand_accesses 51081135 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 12048.344860 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11047.036239 # average overall mshr miss latency
+system.cpu0.icache.demand_hits 50399501 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 8212561500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.013344 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 681634 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 10090564500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.015809 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 914912 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_miss_latency 7530035500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0.013344 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 681634 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 57872551 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 12029.752588 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency
+system.cpu0.icache.overall_accesses 51081135 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 12048.344860 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11047.036239 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 56957639 # number of overall hits
-system.cpu0.icache.overall_miss_latency 11006165000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.015809 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 914912 # number of overall misses
+system.cpu0.icache.overall_hits 50399501 # number of overall hits
+system.cpu0.icache.overall_miss_latency 8212561500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.013344 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 681634 # number of overall misses
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 10090564500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.015809 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 914912 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_miss_latency 7530035500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0.013344 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 681634 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu0.icache.protocol.read_invalid 915158 # read misses to invalid blocks
-system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu0.icache.protocol.snoop_read_exclusive 4652 # read snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
-system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
-system.cpu0.icache.protocol.snoop_read_shared 8768 # read snoops on shared blocks
-system.cpu0.icache.protocol.snoop_readex_exclusive 121 # readEx snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu0.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks
-system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu0.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks
-system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks
-system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks
-system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks
-system.cpu0.icache.replacements 908876 # number of replacements
-system.cpu0.icache.sampled_refs 909388 # Sample count of references to valid blocks.
+system.cpu0.icache.replacements 680987 # number of replacements
+system.cpu0.icache.sampled_refs 681499 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 508.806183 # Cycle average of tags in use
-system.cpu0.icache.total_refs 56957639 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 34906249000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tagsinuse 508.821605 # Cycle average of tags in use
+system.cpu0.icache.total_refs 50399501 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 35300494000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0.943968 # Percentage of idle cycles
-system.cpu0.itb.accesses 3944641 # ITB accesses
-system.cpu0.itb.acv 143 # ITB acv
-system.cpu0.itb.hits 3940800 # ITB hits
-system.cpu0.itb.misses 3841 # ITB misses
-system.cpu0.kern.callpal 187118 # number of callpals executed
+system.cpu0.idle_fraction 0.949890 # Percentage of idle cycles
+system.cpu0.itb.accesses 3593148 # ITB accesses
+system.cpu0.itb.acv 161 # ITB acv
+system.cpu0.itb.hits 3589202 # ITB hits
+system.cpu0.itb.misses 3946 # ITB misses
+system.cpu0.kern.callpal 145952 # number of callpals executed
system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir 96 0.05% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_swpctx 3865 2.07% 2.12% # number of callpals executed
-system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed
-system.cpu0.kern.callpal_wrent 7 0.00% 2.15% # number of callpals executed
-system.cpu0.kern.callpal_swpipl 171254 91.52% 93.67% # number of callpals executed
-system.cpu0.kern.callpal_rdps 6635 3.55% 97.21% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp 1 0.00% 97.21% # number of callpals executed
-system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_rti 4694 2.51% 99.73% # number of callpals executed
-system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed
-system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir 536 0.37% 0.37% # number of callpals executed
+system.cpu0.kern.callpal_wrmces 1 0.00% 0.37% # number of callpals executed
+system.cpu0.kern.callpal_wrfen 1 0.00% 0.37% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.37% # number of callpals executed
+system.cpu0.kern.callpal_swpctx 3014 2.07% 2.44% # number of callpals executed
+system.cpu0.kern.callpal_tbi 46 0.03% 2.47% # number of callpals executed
+system.cpu0.kern.callpal_wrent 7 0.00% 2.47% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 131018 89.77% 92.24% # number of callpals executed
+system.cpu0.kern.callpal_rdps 6493 4.45% 96.69% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp 1 0.00% 96.69% # number of callpals executed
+system.cpu0.kern.callpal_wrusp 4 0.00% 96.69% # number of callpals executed
+system.cpu0.kern.callpal_rdusp 8 0.01% 96.70% # number of callpals executed
+system.cpu0.kern.callpal_whami 2 0.00% 96.70% # number of callpals executed
+system.cpu0.kern.callpal_rti 4302 2.95% 99.65% # number of callpals executed
+system.cpu0.kern.callpal_callsys 368 0.25% 99.90% # number of callpals executed
+system.cpu0.kern.callpal_imb 149 0.10% 100.00% # number of callpals executed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 201983 # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce 6162 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count 178054 # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0 72322 40.62% 40.62% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21 131 0.07% 40.69% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22 1968 1.11% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30 6 0.00% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31 103627 58.20% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good 144005 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0 70953 49.27% 49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22 1968 1.37% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31 70947 49.27% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks 1951128432000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0 1894864204500 97.12% 97.12% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21 72482500 0.00% 97.12% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22 564462000 0.03% 97.15% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30 4114000 0.00% 97.15% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31 55623169000 2.85% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0 0.981071 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.hwrei 161590 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 6598 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count 137863 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0 55298 40.11% 40.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21 131 0.10% 40.21% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22 1969 1.43% 41.63% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30 442 0.32% 41.95% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 80023 58.05% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good 111708 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0 54804 49.06% 49.06% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22 1969 1.76% 50.94% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30 442 0.40% 51.34% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31 54362 48.66% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks 1951366621000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 1898503749000 97.29% 97.29% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21 76310500 0.00% 97.29% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22 547835000 0.03% 97.32% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30 278789500 0.01% 97.34% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 51959937000 2.66% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0 0.991067 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31 0.684638 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel 1230
-system.cpu0.kern.mode_good_user 1231
+system.cpu0.kern.ipl_used_31 0.679330 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1275
+system.cpu0.kern.mode_good_user 1276
system.cpu0.kern.mode_good_idle 0
-system.cpu0.kern.mode_switch_kernel 7215 # number of protection mode switches
-system.cpu0.kern.mode_switch_user 1231 # number of protection mode switches
+system.cpu0.kern.mode_switch_kernel 6846 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1276 # number of protection mode switches
system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel 0.170478 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.186240 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel 1947973402000 99.84% 99.84% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user 3155028000 0.16% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_kernel 1948118613000 99.83% 99.83% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 3248006000 0.17% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3866 # number of times the context was actually changed
-system.cpu0.kern.syscall 224 # number of syscalls executed
-system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed
-system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed
-system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed
-system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed
-system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed
-system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed
-system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed
-system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed
-system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed
-system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed
-system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed
-system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed
-system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed
-system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed
-system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed
-system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed
-system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed
-system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed
-system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed
-system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed
-system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed
-system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed
-system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed
-system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed
-system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed
-system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed
-system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed
-system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed
-system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed
-system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction 0.056032 # Percentage of non-idle cycles
-system.cpu0.numCycles 1951129131000 # number of cpu cycles simulated
-system.cpu0.num_insts 57872550 # Number of instructions executed
-system.cpu0.num_refs 15541096 # Number of memory references
-system.cpu1.dcache.ReadReq_accesses 1052558 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 11119.734481 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10119.576119 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_hits 1014670 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 421304500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.035996 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 37888 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 383410500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035996 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 37888 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable 120 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu1.dcache.ReadResp_mshr_uncacheable_latency 14641500 # number of ReadResp MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_accesses 677186 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 11920.138166 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 10843.231096 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_hits 653157 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 286429000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.035484 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 24029 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 260552000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.035484 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 24029 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable 2496 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu1.dcache.WriteResp_mshr_uncacheable_latency 304596500 # number of WriteResp MSHR uncacheable cycles
+system.cpu0.kern.swap_context 3015 # number of times the context was actually changed
+system.cpu0.kern.syscall 228 # number of syscalls executed
+system.cpu0.kern.syscall_2 7 3.07% 3.07% # number of syscalls executed
+system.cpu0.kern.syscall_3 19 8.33% 11.40% # number of syscalls executed
+system.cpu0.kern.syscall_4 3 1.32% 12.72% # number of syscalls executed
+system.cpu0.kern.syscall_6 31 13.60% 26.32% # number of syscalls executed
+system.cpu0.kern.syscall_12 1 0.44% 26.75% # number of syscalls executed
+system.cpu0.kern.syscall_15 1 0.44% 27.19% # number of syscalls executed
+system.cpu0.kern.syscall_17 10 4.39% 31.58% # number of syscalls executed
+system.cpu0.kern.syscall_19 6 2.63% 34.21% # number of syscalls executed
+system.cpu0.kern.syscall_20 4 1.75% 35.96% # number of syscalls executed
+system.cpu0.kern.syscall_23 2 0.88% 36.84% # number of syscalls executed
+system.cpu0.kern.syscall_24 4 1.75% 38.60% # number of syscalls executed
+system.cpu0.kern.syscall_33 8 3.51% 42.11% # number of syscalls executed
+system.cpu0.kern.syscall_41 2 0.88% 42.98% # number of syscalls executed
+system.cpu0.kern.syscall_45 39 17.11% 60.09% # number of syscalls executed
+system.cpu0.kern.syscall_47 4 1.75% 61.84% # number of syscalls executed
+system.cpu0.kern.syscall_48 8 3.51% 65.35% # number of syscalls executed
+system.cpu0.kern.syscall_54 9 3.95% 69.30% # number of syscalls executed
+system.cpu0.kern.syscall_58 1 0.44% 69.74% # number of syscalls executed
+system.cpu0.kern.syscall_59 6 2.63% 72.37% # number of syscalls executed
+system.cpu0.kern.syscall_71 32 14.04% 86.40% # number of syscalls executed
+system.cpu0.kern.syscall_73 3 1.32% 87.72% # number of syscalls executed
+system.cpu0.kern.syscall_74 9 3.95% 91.67% # number of syscalls executed
+system.cpu0.kern.syscall_87 1 0.44% 92.11% # number of syscalls executed
+system.cpu0.kern.syscall_90 2 0.88% 92.98% # number of syscalls executed
+system.cpu0.kern.syscall_92 7 3.07% 96.05% # number of syscalls executed
+system.cpu0.kern.syscall_97 2 0.88% 96.93% # number of syscalls executed
+system.cpu0.kern.syscall_98 2 0.88% 97.81% # number of syscalls executed
+system.cpu0.kern.syscall_132 2 0.88% 98.68% # number of syscalls executed
+system.cpu0.kern.syscall_144 1 0.44% 99.12% # number of syscalls executed
+system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction 0.050110 # Percentage of non-idle cycles
+system.cpu0.numCycles 1951367346000 # number of cpu cycles simulated
+system.cpu0.num_insts 51081134 # Number of instructions executed
+system.cpu0.num_refs 13268864 # Number of memory references
+system.cpu1.dcache.LoadLockedReq_accesses 61056 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency 9095.192614 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8095.192614 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits 51633 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency 85704000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate 0.154334 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses 9423 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 76281000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.154334 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_misses 9423 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses 2457845 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 11653.965886 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10653.909138 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_hits 2334493 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 1437540000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate 0.050187 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 123352 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency 1314181000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate 0.050187 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses 123352 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 16729500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses 60551 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency 10960.125479 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9960.125479 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits 46206 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency 157223000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate 0.236908 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses 14345 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 142878000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.236908 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_misses 14345 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses 1792743 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 13398.121192 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 12398.121192 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_hits 1700344 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 1237973000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate 0.051541 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 92399 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency 1145574000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate 0.051541 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses 92399 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 421374000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 29.876823 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 23.577992 # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 1729744 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 11430.358383 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 1667827 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 707733500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.035795 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 61917 # number of demand (read+write) misses
+system.cpu1.dcache.demand_accesses 4250588 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 12400.929776 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 11400.897331 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 4034837 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 2675513000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.050758 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 215751 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 643962500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.035795 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 61917 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_miss_latency 2459755000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0.050758 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 215751 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 1729744 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 11430.358383 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 1667827 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 707733500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.035795 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 61917 # number of overall misses
+system.cpu1.dcache.overall_accesses 4250588 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 12400.929776 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 11400.897331 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits 4034837 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 2675513000 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.050758 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 215751 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 643962500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0.035795 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 61917 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 2616 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_miss_latency 2459755000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0.050758 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 215751 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 438103500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu1.dcache.protocol.read_invalid 37951 # read misses to invalid blocks
-system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_read_exclusive 906 # read snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_read_modified 1965 # read snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_read_owned 254 # read snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_read_shared 65869 # read snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_readex_exclusive 191 # readEx snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_readex_modified 198 # readEx snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_readex_owned 48 # readEx snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_readex_shared 42 # readEx snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_upgrade_owned 1132 # upgrade snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_upgrade_shared 2716 # upgradee snoops on shared blocks
-system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu1.dcache.protocol.write_invalid 22206 # write misses to invalid blocks
-system.cpu1.dcache.protocol.write_owned 601 # write misses to owned blocks
-system.cpu1.dcache.protocol.write_shared 1247 # write misses to shared blocks
-system.cpu1.dcache.replacements 55360 # number of replacements
-system.cpu1.dcache.sampled_refs 55749 # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements 176474 # number of replacements
+system.cpu1.dcache.sampled_refs 176909 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 388.749341 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1665603 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1935095598000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 27663 # number of writebacks
-system.cpu1.dtb.accesses 302878 # DTB accesses
-system.cpu1.dtb.acv 84 # DTB access violations
-system.cpu1.dtb.hits 1728432 # DTB hits
-system.cpu1.dtb.misses 3106 # DTB misses
-system.cpu1.dtb.read_accesses 205838 # DTB read accesses
-system.cpu1.dtb.read_acv 36 # DTB read access violations
-system.cpu1.dtb.read_hits 1049360 # DTB read hits
-system.cpu1.dtb.read_misses 2750 # DTB read misses
-system.cpu1.dtb.write_accesses 97040 # DTB write accesses
-system.cpu1.dtb.write_acv 48 # DTB write access violations
-system.cpu1.dtb.write_hits 679072 # DTB write hits
-system.cpu1.dtb.write_misses 356 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 5376264 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 12045.939531 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11045.466957 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 5281041 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 1147050500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.017712 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 95223 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 1051782500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.017712 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 95223 # number of ReadReq MSHR misses
+system.cpu1.dcache.tagsinuse 471.274557 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 4171159 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1917859097000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 93260 # number of writebacks
+system.cpu1.dtb.accesses 296718 # DTB accesses
+system.cpu1.dtb.acv 62 # DTB access violations
+system.cpu1.dtb.hits 4358656 # DTB hits
+system.cpu1.dtb.misses 2867 # DTB misses
+system.cpu1.dtb.read_accesses 201817 # DTB read accesses
+system.cpu1.dtb.read_acv 26 # DTB read access violations
+system.cpu1.dtb.read_hits 2507309 # DTB read hits
+system.cpu1.dtb.read_misses 2546 # DTB read misses
+system.cpu1.dtb.write_accesses 94901 # DTB write accesses
+system.cpu1.dtb.write_acv 36 # DTB write access violations
+system.cpu1.dtb.write_hits 1851347 # DTB write hits
+system.cpu1.dtb.write_misses 321 # DTB write misses
+system.cpu1.icache.ReadReq_accesses 13758345 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 12026.498126 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11026.342473 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits 13421057 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 4056393500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate 0.024515 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 337288 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency 3719053000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate 0.024515 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses 337288 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 57.662729 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 39.794511 # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 5376264 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 12045.939531 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 5281041 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 1147050500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.017712 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 95223 # number of demand (read+write) misses
+system.cpu1.icache.demand_accesses 13758345 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 12026.498126 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11026.342473 # average overall mshr miss latency
+system.cpu1.icache.demand_hits 13421057 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 4056393500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.024515 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 337288 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 1051782500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.017712 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 95223 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_miss_latency 3719053000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0.024515 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 337288 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 5376264 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 12045.939531 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency
+system.cpu1.icache.overall_accesses 13758345 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 12026.498126 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11026.342473 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 5281041 # number of overall hits
-system.cpu1.icache.overall_miss_latency 1147050500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.017712 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 95223 # number of overall misses
+system.cpu1.icache.overall_hits 13421057 # number of overall hits
+system.cpu1.icache.overall_miss_latency 4056393500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.024515 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 337288 # number of overall misses
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 1051782500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.017712 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 95223 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_miss_latency 3719053000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0.024515 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 337288 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu1.icache.protocol.read_invalid 97341 # read misses to invalid blocks
-system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu1.icache.protocol.snoop_read_exclusive 39627 # read snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
-system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
-system.cpu1.icache.protocol.snoop_read_shared 214588 # read snoops on shared blocks
-system.cpu1.icache.protocol.snoop_readex_exclusive 26 # readEx snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
-system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks
-system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks
-system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks
-system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks
-system.cpu1.icache.replacements 91073 # number of replacements
-system.cpu1.icache.sampled_refs 91585 # Sample count of references to valid blocks.
+system.cpu1.icache.replacements 336747 # number of replacements
+system.cpu1.icache.sampled_refs 337259 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 420.500398 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5281041 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1947911714000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tagsinuse 445.859240 # Cycle average of tags in use
+system.cpu1.icache.total_refs 13421057 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1946103109000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0.995322 # Percentage of idle cycles
-system.cpu1.itb.accesses 1399877 # ITB accesses
-system.cpu1.itb.acv 41 # ITB acv
-system.cpu1.itb.hits 1398631 # ITB hits
-system.cpu1.itb.misses 1246 # ITB misses
-system.cpu1.kern.callpal 29847 # number of callpals executed
+system.cpu1.idle_fraction 0.987201 # Percentage of idle cycles
+system.cpu1.itb.accesses 1878768 # ITB accesses
+system.cpu1.itb.acv 23 # ITB acv
+system.cpu1.itb.hits 1877648 # ITB hits
+system.cpu1.itb.misses 1120 # ITB misses
+system.cpu1.kern.callpal 75334 # number of callpals executed
system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed
-system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_swpctx 375 1.26% 1.29% # number of callpals executed
-system.cpu1.kern.callpal_tbi 10 0.03% 1.32% # number of callpals executed
-system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed
-system.cpu1.kern.callpal_swpipl 24461 81.95% 83.30% # number of callpals executed
-system.cpu1.kern.callpal_rdps 2201 7.37% 90.67% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp 1 0.00% 90.68% # number of callpals executed
-system.cpu1.kern.callpal_wrusp 3 0.01% 90.69% # number of callpals executed
-system.cpu1.kern.callpal_rdusp 2 0.01% 90.69% # number of callpals executed
-system.cpu1.kern.callpal_whami 3 0.01% 90.70% # number of callpals executed
-system.cpu1.kern.callpal_rti 2582 8.65% 99.35% # number of callpals executed
-system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed
-system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir 442 0.59% 0.59% # number of callpals executed
+system.cpu1.kern.callpal_wrmces 1 0.00% 0.59% # number of callpals executed
+system.cpu1.kern.callpal_wrfen 1 0.00% 0.59% # number of callpals executed
+system.cpu1.kern.callpal_swpctx 2091 2.78% 3.37% # number of callpals executed
+system.cpu1.kern.callpal_tbi 7 0.01% 3.38% # number of callpals executed
+system.cpu1.kern.callpal_wrent 7 0.01% 3.38% # number of callpals executed
+system.cpu1.kern.callpal_swpipl 66409 88.15% 91.54% # number of callpals executed
+system.cpu1.kern.callpal_rdps 2344 3.11% 94.65% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp 1 0.00% 94.65% # number of callpals executed
+system.cpu1.kern.callpal_wrusp 3 0.00% 94.65% # number of callpals executed
+system.cpu1.kern.callpal_rdusp 1 0.00% 94.66% # number of callpals executed
+system.cpu1.kern.callpal_whami 3 0.00% 94.66% # number of callpals executed
+system.cpu1.kern.callpal_rti 3844 5.10% 99.76% # number of callpals executed
+system.cpu1.kern.callpal_callsys 147 0.20% 99.96% # number of callpals executed
+system.cpu1.kern.callpal_imb 31 0.04% 100.00% # number of callpals executed
system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 36385 # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce 2332 # number of quiesce instructions executed
-system.cpu1.kern.ipl_count 29103 # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0 9344 32.11% 32.11% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22 1963 6.75% 38.85% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30 96 0.33% 39.18% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31 17700 60.82% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good 20635 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0 9336 45.24% 45.24% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22 1963 9.51% 54.76% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30 96 0.47% 55.22% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31 9240 44.78% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks 1950372731000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0 1911409272000 98.00% 98.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22 494740000 0.03% 98.03% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30 52316000 0.00% 98.03% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31 38416403000 1.97% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used_0 0.999144 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.hwrei 81908 # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 72754 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 28089 38.61% 38.61% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22 1964 2.70% 41.31% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30 536 0.74% 42.04% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31 42165 57.96% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good 56376 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 27206 48.26% 48.26% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22 1964 3.48% 51.74% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30 536 0.95% 52.69% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 26670 47.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 1951174446000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 1904796411500 97.62% 97.62% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 499877500 0.03% 97.65% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 327859000 0.02% 97.67% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 45550298000 2.33% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used_0 0.968564 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31 0.522034 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel 538
-system.cpu1.kern.mode_good_user 517
-system.cpu1.kern.mode_good_idle 21
-system.cpu1.kern.mode_switch_kernel 884 # number of protection mode switches
-system.cpu1.kern.mode_switch_user 517 # number of protection mode switches
-system.cpu1.kern.mode_switch_idle 2075 # number of protection mode switches
-system.cpu1.kern.mode_switch_good 1.618718 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel 0.608597 # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used_31 0.632515 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 924
+system.cpu1.kern.mode_good_user 463
+system.cpu1.kern.mode_good_idle 461
+system.cpu1.kern.mode_switch_kernel 2120 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 463 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 2943 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 1.592492 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.435849 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle 0.010120 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel 3563216000 0.18% 0.18% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user 1513259000 0.08% 0.26% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle 1945257297000 99.74% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 376 # number of times the context was actually changed
-system.cpu1.kern.syscall 102 # number of syscalls executed
-system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed
-system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed
-system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed
-system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed
-system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed
-system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed
-system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed
-system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed
-system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed
-system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed
-system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed
-system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed
-system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed
-system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed
-system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed
-system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed
-system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed
-system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed
-system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed
-system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed
-system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction 0.004678 # Percentage of non-idle cycles
-system.cpu1.numCycles 1950372761000 # number of cpu cycles simulated
-system.cpu1.num_insts 5376264 # Number of instructions executed
-system.cpu1.num_refs 1738417 # Number of memory references
+system.cpu1.kern.mode_switch_good_idle 0.156643 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 18594859000 0.95% 0.95% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 1499702000 0.08% 1.03% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 1930131145000 98.97% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 2092 # number of times the context was actually changed
+system.cpu1.kern.syscall 98 # number of syscalls executed
+system.cpu1.kern.syscall_2 1 1.02% 1.02% # number of syscalls executed
+system.cpu1.kern.syscall_3 11 11.22% 12.24% # number of syscalls executed
+system.cpu1.kern.syscall_4 1 1.02% 13.27% # number of syscalls executed
+system.cpu1.kern.syscall_6 11 11.22% 24.49% # number of syscalls executed
+system.cpu1.kern.syscall_17 5 5.10% 29.59% # number of syscalls executed
+system.cpu1.kern.syscall_19 4 4.08% 33.67% # number of syscalls executed
+system.cpu1.kern.syscall_20 2 2.04% 35.71% # number of syscalls executed
+system.cpu1.kern.syscall_23 2 2.04% 37.76% # number of syscalls executed
+system.cpu1.kern.syscall_24 2 2.04% 39.80% # number of syscalls executed
+system.cpu1.kern.syscall_33 3 3.06% 42.86% # number of syscalls executed
+system.cpu1.kern.syscall_45 15 15.31% 58.16% # number of syscalls executed
+system.cpu1.kern.syscall_47 2 2.04% 60.20% # number of syscalls executed
+system.cpu1.kern.syscall_48 2 2.04% 62.24% # number of syscalls executed
+system.cpu1.kern.syscall_54 1 1.02% 63.27% # number of syscalls executed
+system.cpu1.kern.syscall_59 1 1.02% 64.29% # number of syscalls executed
+system.cpu1.kern.syscall_71 22 22.45% 86.73% # number of syscalls executed
+system.cpu1.kern.syscall_74 7 7.14% 93.88% # number of syscalls executed
+system.cpu1.kern.syscall_90 1 1.02% 94.90% # number of syscalls executed
+system.cpu1.kern.syscall_92 2 2.04% 96.94% # number of syscalls executed
+system.cpu1.kern.syscall_132 2 2.04% 98.98% # number of syscalls executed
+system.cpu1.kern.syscall_144 1 1.02% 100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction 0.012799 # Percentage of non-idle cycles
+system.cpu1.numCycles 1951174476000 # number of cpu cycles simulated
+system.cpu1.num_insts 13758345 # Number of instructions executed
+system.cpu1.num_refs 4385954 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.l2c.ReadExReq_accesses 306499 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 12998.029396 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 10997.988681 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits 183694 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 1596223000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 0.400670 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 122805 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 1350608000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 0.400670 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 122805 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2751323 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 12999.901707 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 10999.990968 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits 1810263 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 12233687500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.342039 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 941060 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 10351530500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.342035 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 941049 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable 6993 # number of ReadReq MSHR uncacheable
-system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.l2c.ReadResp_mshr_uncacheable_latency 779629500 # number of ReadResp MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable 12194 # number of WriteReq MSHR uncacheable
-system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.l2c.WriteResp_mshr_uncacheable_latency 1356619000 # number of WriteResp MSHR uncacheable cycles
-system.l2c.Writeback_accesses 429269 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 429256 # number of Writeback hits
-system.l2c.Writeback_miss_rate 0.000030 # miss rate for Writeback accesses
-system.l2c.Writeback_misses 13 # number of Writeback misses
-system.l2c.Writeback_mshr_miss_rate 0.000030 # mshr miss rate for Writeback accesses
-system.l2c.Writeback_mshr_misses 13 # number of Writeback MSHR misses
+system.l2c.ReadExReq_accesses 297979 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 12000.808782 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 11000.808782 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 3575989000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 297979 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 3278010000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 297979 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2726406 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 12000.355770 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 11000.235046 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 1633004 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 13121213000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.401042 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 1093402 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 12027679000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.401042 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 1093402 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 779744500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 125211 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 11388.943463 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 11003.410244 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 1426021000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 125211 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 1377748000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 125211 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1551434500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 416193 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.l2c.Writeback_misses 416193 # number of Writeback misses
+system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.l2c.Writeback_mshr_misses 416193 # number of Writeback MSHR misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 2.277768 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.713697 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2751323 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 12999.901707 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency
-system.l2c.demand_hits 1810263 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 12233687500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.342039 # miss rate for demand accesses
-system.l2c.demand_misses 941060 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 10351530500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.342035 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 941049 # number of demand (read+write) MSHR misses
+system.l2c.demand_accesses 3024385 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 12000.452788 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 11000.357918 # average overall mshr miss latency
+system.l2c.demand_hits 1633004 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 16697202000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.460054 # miss rate for demand accesses
+system.l2c.demand_misses 1391381 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 15305689000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.460054 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 1391381 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3180592 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 12999.722126 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.l2c.overall_hits 2239519 # number of overall hits
-system.l2c.overall_miss_latency 12233687500 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.295880 # miss rate for overall accesses
-system.l2c.overall_misses 941073 # number of overall misses
-system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 10351530500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.295872 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 941049 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 19187 # number of overall MSHR uncacheable misses
+system.l2c.overall_accesses 3024385 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 12000.452788 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 11000.357918 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 1633004 # number of overall hits
+system.l2c.overall_miss_latency 16697202000 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.460054 # miss rate for overall accesses
+system.l2c.overall_misses 1391381 # number of overall misses
+system.l2c.overall_mshr_hits 12 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 15305689000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.460054 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 1391381 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 2331179000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 998318 # number of replacements
-system.l2c.sampled_refs 1063854 # Sample count of references to valid blocks.
+system.l2c.replacements 947502 # number of replacements
+system.l2c.sampled_refs 965785 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 65469.787238 # Cycle average of tags in use
-system.l2c.total_refs 2423213 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 3064127000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 79556 # number of writebacks
+system.l2c.tagsinuse 16369.951624 # Cycle average of tags in use
+system.l2c.total_refs 1655063 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 5421925000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-Listening for system connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
-0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
+Listening for system connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
+0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
-warn: 423901000: Trying to launch CPU number 1!
+warn: 427086000: Trying to launch CPU number 1!
All Rights Reserved
-M5 compiled Jun 10 2007 14:10:03
-M5 started Mon Jun 11 01:30:38 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+M5 compiled Aug 3 2007 04:02:11
+M5 started Fri Aug 3 04:25:10 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-Exiting @ tick 1951129131000 because m5_exit instruction encountered
+Exiting @ tick 1951367346000 because m5_exit instruction encountered
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
profile=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.port[2]
-[system.cpu.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=1
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu.icache.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu.icache_port
mem_side=system.toL2Bus.port[1]
-[system.cpu.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu.itb]
type=AlphaITB
size=48
+[system.cpu.tracer]
+type=ExeTracer
+
[system.disk0]
type=IdeDisk
children=image
[system.l2c]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=8
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=4194304
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
pio_latency=1000
platform=system.tsunami
system=system
-time=2009 1 1 0 0 0 3 1
+time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]
---------- Begin Simulation Statistics ----------
-host_inst_rate 62427 # Simulator instruction rate (inst/s)
-host_seconds 961.73 # Real time elapsed on the host
-host_tick_rate 1983042717 # Simulator tick rate (ticks/s)
+host_inst_rate 631972 # Simulator instruction rate (inst/s)
+host_mem_usage 219140 # Number of bytes of host memory used
+host_seconds 95.00 # Real time elapsed on the host
+host_tick_rate 20109299069 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 60037406 # Number of instructions simulated
-sim_seconds 1.907146 # Number of seconds simulated
-sim_ticks 1907146437000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles
+sim_insts 60034774 # Number of instructions simulated
+sim_seconds 1.910310 # Number of seconds simulated
+sim_ticks 1910309711000 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses 200211 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 13960.656682 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12960.656682 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits 182851 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 242357000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.086709 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 17360 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224997000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086709 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses 17360 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 9525872 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13240.454388 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12240.427719 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits 7801048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 22837453500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.181067 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1724824 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 21112583500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.181067 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1724824 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses 199189 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 14000.798456 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13000.798456 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits 169131 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency 420836000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate 0.150902 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 30058 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 390778000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150902 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses 30058 # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6151132 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 14000.947966 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000.947966 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits 5750801 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5605013500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.065082 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 400331 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5204682500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.065082 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 400331 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164414500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 6.854770 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 15677004 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 13383.714129 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 13551849 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 28442467000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.135559 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2125155 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 26317266000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.135559 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2125155 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 14030883 # number of overall hits
-system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2046000 # number of overall misses
+system.cpu.dcache.overall_accesses 15677004 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 13383.714129 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 13551849 # number of overall hits
+system.cpu.dcache.overall_miss_latency 28442467000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.135559 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2125155 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_miss_latency 26317266000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.135559 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2125155 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 1995240500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks
-system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks
-system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks
-system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks
-system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
-system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks
-system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks
-system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks
-system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks
-system.cpu.dcache.replacements 2045476 # number of replacements
-system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 2046194 # number of replacements
+system.cpu.dcache.sampled_refs 2046706 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 429989 # number of writebacks
+system.cpu.dcache.tagsinuse 511.987834 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14029698 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 58297000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 429991 # number of writebacks
system.cpu.dtb.accesses 1020787 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
-system.cpu.dtb.hits 16057425 # DTB hits
+system.cpu.dtb.hits 16056951 # DTB hits
system.cpu.dtb.misses 11471 # DTB misses
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 9706740 # DTB read hits
+system.cpu.dtb.read_hits 9706492 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_hits 6350685 # DTB write hits
+system.cpu.dtb.write_hits 6350459 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 60034775 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 12033.060657 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.326155 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 59106935 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 11164755000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.015455 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 927840 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 10236233500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.015455 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 927840 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 63.714789 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency
-system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses
-system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 60034775 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 12033.060657 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
+system.cpu.icache.demand_hits 59106935 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 11164755000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.015455 # miss rate for demand accesses
+system.cpu.icache.demand_misses 927840 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 10236233500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.015455 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 927840 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 60034775 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 12033.060657 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 59110217 # number of overall hits
-system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses
-system.cpu.icache.overall_misses 927190 # number of overall misses
+system.cpu.icache.overall_hits 59106935 # number of overall hits
+system.cpu.icache.overall_miss_latency 11164755000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.015455 # miss rate for overall accesses
+system.cpu.icache.overall_misses 927840 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 10236233500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.015455 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 927840 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks
-system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
-system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
-system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks
-system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
-system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
-system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks
-system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
-system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks
-system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks
-system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks
-system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks
-system.cpu.icache.replacements 926519 # number of replacements
-system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 927169 # number of replacements
+system.cpu.icache.sampled_refs 927680 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use
-system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tagsinuse 508.749374 # Cycle average of tags in use
+system.cpu.icache.total_refs 59106935 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 35000367000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0.940784 # Percentage of idle cycles
-system.cpu.itb.accesses 4977586 # ITB accesses
+system.cpu.idle_fraction 0.939637 # Percentage of idle cycles
+system.cpu.itb.accesses 4978395 # ITB accesses
system.cpu.itb.acv 184 # ITB acv
-system.cpu.itb.hits 4972580 # ITB hits
+system.cpu.itb.hits 4973389 # ITB hits
system.cpu.itb.misses 5006 # ITB misses
-system.cpu.kern.callpal 192752 # number of callpals executed
+system.cpu.kern.callpal 192813 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed
-system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed
+system.cpu.kern.callpal_swpipl 175877 91.22% 93.42% # number of callpals executed
+system.cpu.kern.callpal_rdps 6828 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
-system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed
+system.cpu.kern.callpal_rti 5152 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei 211901 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed
-system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl
+system.cpu.kern.ipl_count 183088 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 74875 40.90% 40.90% # number of times we switched to this ipl
system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count_22 1927 1.05% 42.02% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 106155 57.98% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 149074 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 73508 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good_22 1927 1.29% 50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 73508 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 1910308997000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1853401678500 97.02% 97.02% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 78202500 0.00% 97.03% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 538133000 0.03% 97.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 56290983000 2.95% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0 0.981743 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel 1910
-system.cpu.kern.mode_good_user 1740
+system.cpu.kern.ipl_used_31 0.692459 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1908
+system.cpu.kern.mode_good_user 1738
system.cpu.kern.mode_good_idle 170
-system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches
-system.cpu.kern.mode_switch_user 1740 # number of protection mode switches
-system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches
-system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_kernel 5896 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2098 # number of protection mode switches
+system.cpu.kern.mode_switch_good 1.404639 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.323609 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good_idle 0.081030 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 43115749000 2.26% 2.26% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 4716926000 0.25% 2.50% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1862476320000 97.50% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles
-system.cpu.numCycles 1907146437000 # number of cpu cycles simulated
-system.cpu.num_insts 60037406 # Number of instructions executed
-system.cpu.num_refs 16305563 # Number of memory references
+system.cpu.not_idle_fraction 0.060363 # Percentage of non-idle cycles
+system.cpu.numCycles 1910309711000 # number of cpu cycles simulated
+system.cpu.num_insts 60034774 # Number of instructions executed
+system.cpu.num_refs 16305091 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits 1727874 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 940980 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable
-system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable
-system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles
-system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 429989 # number of Writeback hits
+system.l2c.ReadExReq_accesses 304522 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 12000.719160 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 11000.719160 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 3654483000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 304522 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 3349961000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 304522 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2670005 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 12000.233269 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 11000.233269 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 1568273 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 13221041000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.412633 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 1101732 # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency 12119309000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.412633 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 1101732 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 125867 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 11999.892744 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 11000.750793 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 1510390500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 125867 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 1384631500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 125867 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1051110500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 429991 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.l2c.Writeback_misses 429991 # number of Writeback misses
+system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.l2c.Writeback_mshr_misses 429991 # number of Writeback MSHR misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 2.216875 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.660842 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency
-system.l2c.demand_hits 1727874 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses
-system.l2c.demand_misses 940980 # number of demand (read+write) misses
+system.l2c.demand_accesses 2974527 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 12000.338488 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
+system.l2c.demand_hits 1568273 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 16875524000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.472766 # miss rate for demand accesses
+system.l2c.demand_misses 1406254 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency 15469270000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.472766 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 1406254 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.l2c.overall_hits 2157863 # number of overall hits
-system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses
-system.l2c.overall_misses 940980 # number of overall misses
+system.l2c.overall_accesses 2974527 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 12000.338488 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 1568273 # number of overall hits
+system.l2c.overall_miss_latency 16875524000 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.472766 # miss rate for overall accesses
+system.l2c.overall_misses 1406254 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_miss_latency 15469270000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.472766 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 1406254 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1801212500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 992369 # number of replacements
-system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks.
+system.l2c.replacements 947259 # number of replacements
+system.l2c.sampled_refs 965538 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use
-system.l2c.total_refs 2345243 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 74072 # number of writebacks
+system.l2c.tagsinuse 15874.904757 # Cycle average of tags in use
+system.l2c.total_refs 1603606 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 4106790000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-Listening for system connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+Listening for system connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
All Rights Reserved
-M5 compiled Jun 10 2007 14:10:03
-M5 started Mon Jun 11 01:14:34 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+M5 compiled Aug 3 2007 04:02:11
+M5 started Fri Aug 3 04:23:34 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-Exiting @ tick 1907146437000 because m5_exit instruction encountered
+Exiting @ tick 1910309711000 because m5_exit instruction encountered
[system.cpu0.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu0.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu0.test
mem_side=system.toL2Bus.port[1]
-[system.cpu0.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu1]
type=MemTest
children=l1c
[system.cpu1.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu1.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu1.test
mem_side=system.toL2Bus.port[2]
-[system.cpu1.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu2]
type=MemTest
children=l1c
[system.cpu2.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu2.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu2.test
mem_side=system.toL2Bus.port[3]
-[system.cpu2.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu3]
type=MemTest
children=l1c
[system.cpu3.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu3.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu3.test
mem_side=system.toL2Bus.port[4]
-[system.cpu3.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu4]
type=MemTest
children=l1c
[system.cpu4.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu4.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu4.test
mem_side=system.toL2Bus.port[5]
-[system.cpu4.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu5]
type=MemTest
children=l1c
[system.cpu5.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu5.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu5.test
mem_side=system.toL2Bus.port[6]
-[system.cpu5.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu6]
type=MemTest
children=l1c
[system.cpu6.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu6.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu6.test
mem_side=system.toL2Bus.port[7]
-[system.cpu6.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.cpu7]
type=MemTest
children=l1c
[system.cpu7.l1c]
type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=4
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=1000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=system.cpu7.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
cpu_side=system.cpu7.test
mem_side=system.toL2Bus.port[8]
-[system.cpu7.l1c.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
[system.funcmem]
type=PhysicalMemory
file=
[system.l2c]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=8
block_size=64
-compressed_bus=false
-compression_latency=0
hash_delay=1
latency=10000
lifo=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=65536
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
---------- Begin Simulation Statistics ----------
-host_seconds 37943.64 # Real time elapsed on the host
-host_tick_rate 2223 # Simulator tick rate (ticks/s)
+host_mem_usage 318912 # Number of bytes of host memory used
+host_seconds 272.84 # Real time elapsed on the host
+host_tick_rate 598087 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_seconds 0.000084 # Number of seconds simulated
-sim_ticks 84350509 # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses 44421 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 14010.391786 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 12986.475734 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_hits 7291 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency 520205847 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate 0.835866 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses 37130 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency 482187844 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835866 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses 37130 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable 9916 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 255520881 # number of ReadResp MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses 23898 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 12904.605270 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 11399.917485 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_hits 1090 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency 294328237 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate 0.954389 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses 22808 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency 260009318 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate 0.954389 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses 22808 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable 5184 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 154702333 # number of WriteResp MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1194.948852 # average number of cycles each access was blocked
+sim_seconds 0.000163 # Number of seconds simulated
+sim_ticks 163182312 # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses 44955 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 22713.586650 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 22705.587882 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_hits 7621 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency 847989044 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate 0.830475 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses 37334 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency 847690418 # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate 0.830475 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses 37334 # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 517943783 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses 24357 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 24775.291654 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 24768.103842 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_hits 956 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency 579766600 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate 0.960751 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses 23401 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency 579598398 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate 0.960751 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses 23401 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 315492846 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles_no_mshrs 2283.512556 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs 0.407238 # Average number of references to valid blocks.
-system.cpu0.l1c.blocked_no_mshrs 69093 # number of cycles access was blocked
+system.cpu0.l1c.avg_refs 0.411295 # Average number of references to valid blocks.
+system.cpu0.l1c.blocked_no_mshrs 69290 # number of cycles access was blocked
system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles_no_mshrs 82562601 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_mshrs 158224585 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.demand_accesses 68319 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency 13589.610664 # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency
-system.cpu0.l1c.demand_hits 8381 # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency 814534084 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate 0.877325 # miss rate for demand accesses
-system.cpu0.l1c.demand_misses 59938 # number of demand (read+write) misses
+system.cpu0.l1c.demand_accesses 69312 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency 23507.954952 # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 23500.268642 # average overall mshr miss latency
+system.cpu0.l1c.demand_hits 8577 # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency 1427755644 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate 0.876255 # miss rate for demand accesses
+system.cpu0.l1c.demand_misses 60735 # number of demand (read+write) misses
system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency 742197162 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate 0.877325 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses 59938 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_miss_latency 1427288816 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate 0.876255 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses 60735 # number of demand (read+write) MSHR misses
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.l1c.overall_accesses 68319 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 13589.610664 # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits 8381 # number of overall hits
-system.cpu0.l1c.overall_miss_latency 814534084 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate 0.877325 # miss rate for overall accesses
-system.cpu0.l1c.overall_misses 59938 # number of overall misses
+system.cpu0.l1c.overall_accesses 69312 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 23507.954952 # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 23500.268642 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_hits 8577 # number of overall hits
+system.cpu0.l1c.overall_miss_latency 1427755644 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_rate 0.876255 # miss rate for overall accesses
+system.cpu0.l1c.overall_misses 60735 # number of overall misses
system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency 742197162 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate 0.877325 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses 59938 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_misses 15100 # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_miss_latency 1427288816 # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate 0.876255 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses 60735 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_latency 833436629 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu0.l1c.protocol.read_invalid 1761660 # read misses to invalid blocks
-system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu0.l1c.protocol.snoop_read_exclusive 2836 # read snoops on exclusive blocks
-system.cpu0.l1c.protocol.snoop_read_modified 12378 # read snoops on modified blocks
-system.cpu0.l1c.protocol.snoop_read_owned 7300 # read snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_read_shared 1749577 # read snoops on shared blocks
-system.cpu0.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks
-system.cpu0.l1c.protocol.snoop_readex_modified 6692 # readEx snoops on modified blocks
-system.cpu0.l1c.protocol.snoop_readex_owned 4009 # readEx snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_readex_shared 12550 # readEx snoops on shared blocks
-system.cpu0.l1c.protocol.snoop_upgrade_owned 790 # upgrade snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_upgrade_shared 3004 # upgradee snoops on shared blocks
-system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu0.l1c.protocol.write_invalid 940728 # write misses to invalid blocks
-system.cpu0.l1c.protocol.write_owned 1344 # write misses to owned blocks
-system.cpu0.l1c.protocol.write_shared 4484 # write misses to shared blocks
-system.cpu0.l1c.replacements 27160 # number of replacements
-system.cpu0.l1c.sampled_refs 27495 # Sample count of references to valid blocks.
+system.cpu0.l1c.replacements 28052 # number of replacements
+system.cpu0.l1c.sampled_refs 28403 # Sample count of references to valid blocks.
system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse 342.709273 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 11197 # Total number of references to valid blocks.
+system.cpu0.l1c.tagsinuse 348.576200 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 11682 # Total number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks 10716 # number of writebacks
+system.cpu0.l1c.writebacks 11146 # number of writebacks
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.num_reads 98012 # number of read accesses completed
-system.cpu0.num_writes 53207 # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses 44893 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 13909.754864 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 12900.185775 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_hits 7579 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency 519028593 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate 0.831176 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_misses 37314 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency 481357532 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831176 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_misses 37314 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable 9811 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 251708747 # number of ReadResp MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_accesses 24614 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_avg_miss_latency 12788.679753 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 11344.205121 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_hits 1257 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_miss_latency 298705193 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_rate 0.948932 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_misses 23357 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_mshr_miss_latency 264966599 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_rate 0.948932 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_misses 23357 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_uncacheable 5453 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 163813954 # number of WriteResp MSHR uncacheable cycles
-system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1183.149435 # average number of cycles each access was blocked
+system.cpu0.num_reads 99892 # number of read accesses completed
+system.cpu0.num_writes 54159 # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses 44788 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_avg_miss_latency 22745.661074 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 22737.662205 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_hits 7659 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_miss_latency 844523650 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_rate 0.828994 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_misses 37129 # number of ReadReq misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency 844226660 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate 0.828994 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_misses 37129 # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 524670355 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_accesses 24323 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_avg_miss_latency 24767.283276 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 24760.081804 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_hits 950 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_miss_latency 578885712 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_rate 0.960942 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_misses 23373 # number of WriteReq misses
+system.cpu1.l1c.WriteReq_mshr_miss_latency 578717392 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_rate 0.960942 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_misses 23373 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 319087206 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.avg_blocked_cycles_no_mshrs 2291.446711 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.l1c.avg_refs 0.414323 # Average number of references to valid blocks.
-system.cpu1.l1c.blocked_no_mshrs 69763 # number of cycles access was blocked
+system.cpu1.l1c.avg_refs 0.414757 # Average number of references to valid blocks.
+system.cpu1.l1c.blocked_no_mshrs 69358 # number of cycles access was blocked
system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles_no_mshrs 82540054 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_mshrs 158930161 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.demand_accesses 69507 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_avg_miss_latency 13478.165615 # average overall miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency
-system.cpu1.l1c.demand_hits 8836 # number of demand (read+write) hits
-system.cpu1.l1c.demand_miss_latency 817733786 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_rate 0.872876 # miss rate for demand accesses
-system.cpu1.l1c.demand_misses 60671 # number of demand (read+write) misses
+system.cpu1.l1c.demand_accesses 69111 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_avg_miss_latency 23526.649731 # average overall miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 23518.958910 # average overall mshr miss latency
+system.cpu1.l1c.demand_hits 8609 # number of demand (read+write) hits
+system.cpu1.l1c.demand_miss_latency 1423409362 # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_rate 0.875432 # miss rate for demand accesses
+system.cpu1.l1c.demand_misses 60502 # number of demand (read+write) misses
system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.l1c.demand_mshr_miss_latency 746324131 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_rate 0.872876 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_misses 60671 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_miss_latency 1422944052 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_rate 0.875432 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_misses 60502 # number of demand (read+write) MSHR misses
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.l1c.overall_accesses 69507 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_avg_miss_latency 13478.165615 # average overall miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_hits 8836 # number of overall hits
-system.cpu1.l1c.overall_miss_latency 817733786 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_rate 0.872876 # miss rate for overall accesses
-system.cpu1.l1c.overall_misses 60671 # number of overall misses
+system.cpu1.l1c.overall_accesses 69111 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_avg_miss_latency 23526.649731 # average overall miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 23518.958910 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_hits 8609 # number of overall hits
+system.cpu1.l1c.overall_miss_latency 1423409362 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_rate 0.875432 # miss rate for overall accesses
+system.cpu1.l1c.overall_misses 60502 # number of overall misses
system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.l1c.overall_mshr_miss_latency 746324131 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_rate 0.872876 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_misses 60671 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_misses 15264 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_miss_latency 1422944052 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_rate 0.875432 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_misses 60502 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_latency 843757561 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu1.l1c.protocol.read_invalid 1717891 # read misses to invalid blocks
-system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu1.l1c.protocol.snoop_read_exclusive 2925 # read snoops on exclusive blocks
-system.cpu1.l1c.protocol.snoop_read_modified 12701 # read snoops on modified blocks
-system.cpu1.l1c.protocol.snoop_read_owned 7436 # read snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_read_shared 1669937 # read snoops on shared blocks
-system.cpu1.l1c.protocol.snoop_readex_exclusive 1611 # readEx snoops on exclusive blocks
-system.cpu1.l1c.protocol.snoop_readex_modified 6726 # readEx snoops on modified blocks
-system.cpu1.l1c.protocol.snoop_readex_owned 3965 # readEx snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_readex_shared 12596 # readEx snoops on shared blocks
-system.cpu1.l1c.protocol.snoop_upgrade_owned 860 # upgrade snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_upgrade_shared 2979 # upgradee snoops on shared blocks
-system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu1.l1c.protocol.write_invalid 914774 # write misses to invalid blocks
-system.cpu1.l1c.protocol.write_owned 1422 # write misses to owned blocks
-system.cpu1.l1c.protocol.write_shared 4382 # write misses to shared blocks
-system.cpu1.l1c.replacements 27806 # number of replacements
-system.cpu1.l1c.sampled_refs 28164 # Sample count of references to valid blocks.
+system.cpu1.l1c.replacements 27765 # number of replacements
+system.cpu1.l1c.sampled_refs 28108 # Sample count of references to valid blocks.
system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.l1c.tagsinuse 345.545872 # Cycle average of tags in use
-system.cpu1.l1c.total_refs 11669 # Total number of references to valid blocks.
+system.cpu1.l1c.tagsinuse 346.327274 # Cycle average of tags in use
+system.cpu1.l1c.total_refs 11658 # Total number of references to valid blocks.
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.writebacks 11204 # number of writebacks
+system.cpu1.l1c.writebacks 10962 # number of writebacks
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 100000 # number of read accesses completed
-system.cpu1.num_writes 54335 # number of write accesses completed
-system.cpu2.l1c.ReadReq_accesses 44489 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_avg_miss_latency 14018.031231 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 12993.788573 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_hits 7507 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_miss_latency 518414831 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_rate 0.831262 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_misses 36982 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency 480536289 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate 0.831262 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_misses 36982 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 253484666 # number of ReadResp MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_accesses 24340 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_avg_miss_latency 12765.385606 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 11318.971789 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_hits 1122 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_miss_latency 296386723 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_rate 0.953903 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_misses 23218 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_mshr_miss_latency 262803887 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_rate 0.953903 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_misses 23218 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_uncacheable 5480 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 165110755 # number of WriteResp MSHR uncacheable cycles
-system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1190.317505 # average number of cycles each access was blocked
+system.cpu1.num_reads 99692 # number of read accesses completed
+system.cpu1.num_writes 53844 # number of write accesses completed
+system.cpu2.l1c.ReadReq_accesses 45045 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_avg_miss_latency 22675.185062 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 22667.185702 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_hits 7544 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_miss_latency 850342115 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_rate 0.832523 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_misses 37501 # number of ReadReq misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency 850042131 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832523 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_misses 37501 # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 526690736 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_accesses 23975 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_avg_miss_latency 24810.638326 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 24803.479873 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_hits 946 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_miss_latency 571364190 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_rate 0.960542 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_misses 23029 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_mshr_miss_latency 571199338 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_rate 0.960542 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_misses 23029 # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 314108208 # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.avg_blocked_cycles_no_mshrs 2295.331392 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.l1c.avg_refs 0.414721 # Average number of references to valid blocks.
-system.cpu2.l1c.blocked_no_mshrs 69202 # number of cycles access was blocked
+system.cpu2.l1c.avg_refs 0.417132 # Average number of references to valid blocks.
+system.cpu2.l1c.blocked_no_mshrs 69383 # number of cycles access was blocked
system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles_no_mshrs 82372352 # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_mshrs 159256978 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.demand_accesses 68829 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_avg_miss_latency 13534.909535 # average overall miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency
-system.cpu2.l1c.demand_hits 8629 # number of demand (read+write) hits
-system.cpu2.l1c.demand_miss_latency 814801554 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_rate 0.874631 # miss rate for demand accesses
-system.cpu2.l1c.demand_misses 60200 # number of demand (read+write) misses
+system.cpu2.l1c.demand_accesses 69020 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_avg_miss_latency 23487.631009 # average overall miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 23479.951578 # average overall mshr miss latency
+system.cpu2.l1c.demand_hits 8490 # number of demand (read+write) hits
+system.cpu2.l1c.demand_miss_latency 1421706305 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_rate 0.876992 # miss rate for demand accesses
+system.cpu2.l1c.demand_misses 60530 # number of demand (read+write) misses
system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.l1c.demand_mshr_miss_latency 743340176 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_rate 0.874631 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_misses 60200 # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_miss_latency 1421241469 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_rate 0.876992 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_misses 60530 # number of demand (read+write) MSHR misses
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.l1c.overall_accesses 68829 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_avg_miss_latency 13534.909535 # average overall miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_hits 8629 # number of overall hits
-system.cpu2.l1c.overall_miss_latency 814801554 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_rate 0.874631 # miss rate for overall accesses
-system.cpu2.l1c.overall_misses 60200 # number of overall misses
+system.cpu2.l1c.overall_accesses 69020 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_avg_miss_latency 23487.631009 # average overall miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 23479.951578 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_hits 8490 # number of overall hits
+system.cpu2.l1c.overall_miss_latency 1421706305 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_rate 0.876992 # miss rate for overall accesses
+system.cpu2.l1c.overall_misses 60530 # number of overall misses
system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.l1c.overall_mshr_miss_latency 743340176 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_rate 0.874631 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_misses 60200 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_misses 15341 # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_miss_latency 1421241469 # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_rate 0.876992 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_misses 60530 # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_latency 840798944 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu2.l1c.protocol.read_invalid 1818161 # read misses to invalid blocks
-system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu2.l1c.protocol.snoop_read_exclusive 2846 # read snoops on exclusive blocks
-system.cpu2.l1c.protocol.snoop_read_modified 12505 # read snoops on modified blocks
-system.cpu2.l1c.protocol.snoop_read_owned 7354 # read snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_read_shared 1719896 # read snoops on shared blocks
-system.cpu2.l1c.protocol.snoop_readex_exclusive 1512 # readEx snoops on exclusive blocks
-system.cpu2.l1c.protocol.snoop_readex_modified 6836 # readEx snoops on modified blocks
-system.cpu2.l1c.protocol.snoop_readex_owned 4066 # readEx snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_readex_shared 12494 # readEx snoops on shared blocks
-system.cpu2.l1c.protocol.snoop_upgrade_owned 828 # upgrade snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_upgrade_shared 2975 # upgradee snoops on shared blocks
-system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu2.l1c.protocol.write_invalid 1061132 # write misses to invalid blocks
-system.cpu2.l1c.protocol.write_owned 1410 # write misses to owned blocks
-system.cpu2.l1c.protocol.write_shared 4436 # write misses to shared blocks
-system.cpu2.l1c.replacements 27337 # number of replacements
-system.cpu2.l1c.sampled_refs 27674 # Sample count of references to valid blocks.
+system.cpu2.l1c.replacements 27570 # number of replacements
+system.cpu2.l1c.sampled_refs 27912 # Sample count of references to valid blocks.
system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.l1c.tagsinuse 343.290844 # Cycle average of tags in use
-system.cpu2.l1c.total_refs 11477 # Total number of references to valid blocks.
+system.cpu2.l1c.tagsinuse 346.579014 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 11643 # Total number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.writebacks 10872 # number of writebacks
+system.cpu2.l1c.writebacks 10678 # number of writebacks
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 98887 # number of read accesses completed
-system.cpu2.num_writes 53640 # number of write accesses completed
-system.cpu3.l1c.ReadReq_accesses 44566 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_avg_miss_latency 14066.553951 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 13052.525235 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_hits 7375 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_miss_latency 523149208 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_rate 0.834515 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_misses 37191 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency 485436466 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834515 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 252799971 # number of ReadResp MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_accesses 24030 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_avg_miss_latency 12807.474484 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 11345.837164 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_hits 1142 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_miss_latency 293137476 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_rate 0.952476 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_misses 22888 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_mshr_miss_latency 259683521 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_rate 0.952476 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_misses 22888 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_uncacheable 5294 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 159218905 # number of WriteResp MSHR uncacheable cycles
-system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1193.729049 # average number of cycles each access was blocked
+system.cpu2.num_reads 99982 # number of read accesses completed
+system.cpu2.num_writes 53451 # number of write accesses completed
+system.cpu3.l1c.ReadReq_accesses 45026 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_avg_miss_latency 22627.689991 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 22619.691218 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_hits 7540 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_miss_latency 848221587 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_rate 0.832541 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_misses 37486 # number of ReadReq misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency 847921745 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate 0.832541 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_misses 37486 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 521058272 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_accesses 24496 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_avg_miss_latency 24499.134103 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 24491.950730 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_hits 932 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_miss_latency 577297596 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_rate 0.961953 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_misses 23564 # number of WriteReq misses
+system.cpu3.l1c.WriteReq_mshr_miss_latency 577128327 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961953 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_misses 23564 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 316556554 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.avg_blocked_cycles_no_mshrs 2277.071019 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.l1c.avg_refs 0.411345 # Average number of references to valid blocks.
-system.cpu3.l1c.blocked_no_mshrs 69160 # number of cycles access was blocked
+system.cpu3.l1c.avg_refs 0.408241 # Average number of references to valid blocks.
+system.cpu3.l1c.blocked_no_mshrs 69700 # number of cycles access was blocked
system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles_no_mshrs 82558301 # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_mshrs 158711850 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.demand_accesses 68596 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_avg_miss_latency 13586.888663 # average overall miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency
-system.cpu3.l1c.demand_hits 8517 # number of demand (read+write) hits
-system.cpu3.l1c.demand_miss_latency 816286684 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_rate 0.875838 # miss rate for demand accesses
-system.cpu3.l1c.demand_misses 60079 # number of demand (read+write) misses
+system.cpu3.l1c.demand_accesses 69522 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_avg_miss_latency 23350.027568 # average overall miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 23342.343522 # average overall mshr miss latency
+system.cpu3.l1c.demand_hits 8472 # number of demand (read+write) hits
+system.cpu3.l1c.demand_miss_latency 1425519183 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_rate 0.878139 # miss rate for demand accesses
+system.cpu3.l1c.demand_misses 61050 # number of demand (read+write) misses
system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.l1c.demand_mshr_miss_latency 745119987 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_rate 0.875838 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_misses 60079 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_miss_latency 1425050072 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_rate 0.878139 # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_misses 61050 # number of demand (read+write) MSHR misses
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.l1c.overall_accesses 68596 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_avg_miss_latency 13586.888663 # average overall miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_hits 8517 # number of overall hits
-system.cpu3.l1c.overall_miss_latency 816286684 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_rate 0.875838 # miss rate for overall accesses
-system.cpu3.l1c.overall_misses 60079 # number of overall misses
+system.cpu3.l1c.overall_accesses 69522 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_avg_miss_latency 23350.027568 # average overall miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 23342.343522 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_hits 8472 # number of overall hits
+system.cpu3.l1c.overall_miss_latency 1425519183 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_rate 0.878139 # miss rate for overall accesses
+system.cpu3.l1c.overall_misses 61050 # number of overall misses
system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.l1c.overall_mshr_miss_latency 745119987 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_rate 0.875838 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_misses 60079 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_misses 15114 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_miss_latency 1425050072 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_rate 0.878139 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_misses 61050 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_latency 837614826 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu3.l1c.protocol.read_invalid 1894373 # read misses to invalid blocks
-system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu3.l1c.protocol.snoop_read_exclusive 2902 # read snoops on exclusive blocks
-system.cpu3.l1c.protocol.snoop_read_modified 12291 # read snoops on modified blocks
-system.cpu3.l1c.protocol.snoop_read_owned 7221 # read snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_read_shared 1743434 # read snoops on shared blocks
-system.cpu3.l1c.protocol.snoop_readex_exclusive 1553 # readEx snoops on exclusive blocks
-system.cpu3.l1c.protocol.snoop_readex_modified 6822 # readEx snoops on modified blocks
-system.cpu3.l1c.protocol.snoop_readex_owned 3914 # readEx snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_readex_shared 12477 # readEx snoops on shared blocks
-system.cpu3.l1c.protocol.snoop_upgrade_owned 867 # upgrade snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_upgrade_shared 3008 # upgradee snoops on shared blocks
-system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu3.l1c.protocol.write_invalid 1046634 # write misses to invalid blocks
-system.cpu3.l1c.protocol.write_owned 1364 # write misses to owned blocks
-system.cpu3.l1c.protocol.write_shared 4484 # write misses to shared blocks
-system.cpu3.l1c.replacements 27286 # number of replacements
-system.cpu3.l1c.sampled_refs 27624 # Sample count of references to valid blocks.
+system.cpu3.l1c.replacements 28153 # number of replacements
+system.cpu3.l1c.sampled_refs 28515 # Sample count of references to valid blocks.
system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.l1c.tagsinuse 342.290575 # Cycle average of tags in use
-system.cpu3.l1c.total_refs 11363 # Total number of references to valid blocks.
+system.cpu3.l1c.tagsinuse 348.493440 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 11641 # Total number of references to valid blocks.
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.writebacks 10681 # number of writebacks
+system.cpu3.l1c.writebacks 11085 # number of writebacks
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 99322 # number of read accesses completed
-system.cpu3.num_writes 53280 # number of write accesses completed
-system.cpu4.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_avg_miss_latency 13943.186039 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 12937.718615 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_hits 7581 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_miss_latency 521335726 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_rate 0.831425 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_misses 37390 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency 483741299 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831425 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable 9931 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 254015216 # number of ReadResp MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_accesses 24134 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_avg_miss_latency 12764.573629 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 11273.971841 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_hits 1086 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_miss_latency 294197893 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_rate 0.955001 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_misses 23048 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_mshr_miss_latency 259842503 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_rate 0.955001 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_misses 23048 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_uncacheable 5390 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 161643344 # number of WriteResp MSHR uncacheable cycles
-system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1186.636056 # average number of cycles each access was blocked
+system.cpu3.num_reads 99697 # number of read accesses completed
+system.cpu3.num_writes 54254 # number of write accesses completed
+system.cpu4.l1c.ReadReq_accesses 44695 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_avg_miss_latency 22595.724111 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 22587.725051 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_hits 7459 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_miss_latency 841374383 # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_rate 0.833113 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_misses 37236 # number of ReadReq misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency 841076530 # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833113 # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_misses 37236 # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 521925270 # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_accesses 24320 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_avg_miss_latency 24976.967619 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 24969.752460 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_hits 942 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_miss_latency 583911549 # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_rate 0.961266 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_misses 23378 # number of WriteReq misses
+system.cpu4.l1c.WriteReq_mshr_miss_latency 583742873 # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_rate 0.961266 # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_misses 23378 # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 314744590 # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.avg_blocked_cycles_no_mshrs 2286.910395 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu4.l1c.avg_refs 0.410931 # Average number of references to valid blocks.
-system.cpu4.l1c.blocked_no_mshrs 69637 # number of cycles access was blocked
+system.cpu4.l1c.avg_refs 0.401516 # Average number of references to valid blocks.
+system.cpu4.l1c.blocked_no_mshrs 69382 # number of cycles access was blocked
system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles_no_mshrs 82633775 # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_mshrs 158670417 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.demand_accesses 69105 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_avg_miss_latency 13493.722807 # average overall miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency
-system.cpu4.l1c.demand_hits 8667 # number of demand (read+write) hits
-system.cpu4.l1c.demand_miss_latency 815533619 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_rate 0.874582 # miss rate for demand accesses
-system.cpu4.l1c.demand_misses 60438 # number of demand (read+write) misses
+system.cpu4.l1c.demand_accesses 69015 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_avg_miss_latency 23514.137526 # average overall miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 23506.440806 # average overall mshr miss latency
+system.cpu4.l1c.demand_hits 8401 # number of demand (read+write) hits
+system.cpu4.l1c.demand_miss_latency 1425285932 # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_rate 0.878273 # miss rate for demand accesses
+system.cpu4.l1c.demand_misses 60614 # number of demand (read+write) misses
system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu4.l1c.demand_mshr_miss_latency 743583802 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_rate 0.874582 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_misses 60438 # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_miss_latency 1424819403 # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_rate 0.878273 # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_misses 60614 # number of demand (read+write) MSHR misses
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.l1c.overall_accesses 69105 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_avg_miss_latency 13493.722807 # average overall miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_hits 8667 # number of overall hits
-system.cpu4.l1c.overall_miss_latency 815533619 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_rate 0.874582 # miss rate for overall accesses
-system.cpu4.l1c.overall_misses 60438 # number of overall misses
+system.cpu4.l1c.overall_accesses 69015 # number of overall (read+write) accesses
+system.cpu4.l1c.overall_avg_miss_latency 23514.137526 # average overall miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 23506.440806 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_hits 8401 # number of overall hits
+system.cpu4.l1c.overall_miss_latency 1425285932 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_rate 0.878273 # miss rate for overall accesses
+system.cpu4.l1c.overall_misses 60614 # number of overall misses
system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu4.l1c.overall_mshr_miss_latency 743583802 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_rate 0.874582 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_misses 60438 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_misses 15321 # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_miss_latency 1424819403 # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_rate 0.878273 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_misses 60614 # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_latency 836669860 # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu4.l1c.protocol.read_invalid 1830675 # read misses to invalid blocks
-system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu4.l1c.protocol.snoop_read_exclusive 2847 # read snoops on exclusive blocks
-system.cpu4.l1c.protocol.snoop_read_modified 12499 # read snoops on modified blocks
-system.cpu4.l1c.protocol.snoop_read_owned 7458 # read snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_read_shared 1765770 # read snoops on shared blocks
-system.cpu4.l1c.protocol.snoop_readex_exclusive 1560 # readEx snoops on exclusive blocks
-system.cpu4.l1c.protocol.snoop_readex_modified 6711 # readEx snoops on modified blocks
-system.cpu4.l1c.protocol.snoop_readex_owned 3919 # readEx snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_readex_shared 12526 # readEx snoops on shared blocks
-system.cpu4.l1c.protocol.snoop_upgrade_owned 902 # upgrade snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_upgrade_shared 3023 # upgradee snoops on shared blocks
-system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu4.l1c.protocol.write_invalid 854606 # write misses to invalid blocks
-system.cpu4.l1c.protocol.write_owned 1318 # write misses to owned blocks
-system.cpu4.l1c.protocol.write_shared 4519 # write misses to shared blocks
-system.cpu4.l1c.replacements 27664 # number of replacements
-system.cpu4.l1c.sampled_refs 28012 # Sample count of references to valid blocks.
+system.cpu4.l1c.replacements 28031 # number of replacements
+system.cpu4.l1c.sampled_refs 28370 # Sample count of references to valid blocks.
system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu4.l1c.tagsinuse 344.185288 # Cycle average of tags in use
-system.cpu4.l1c.total_refs 11511 # Total number of references to valid blocks.
+system.cpu4.l1c.tagsinuse 347.544315 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 11391 # Total number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.writebacks 10935 # number of writebacks
+system.cpu4.l1c.writebacks 11138 # number of writebacks
system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 99841 # number of read accesses completed
-system.cpu4.num_writes 54005 # number of write accesses completed
-system.cpu5.l1c.ReadReq_accesses 45075 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_avg_miss_latency 13980.675167 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 12974.186518 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_hits 7588 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_miss_latency 524093570 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_rate 0.831658 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_misses 37487 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency 486363330 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831658 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable 9769 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 252483534 # number of ReadResp MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_accesses 24120 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_avg_miss_latency 12733.111936 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 11249.826210 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_hits 1098 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_miss_latency 293141703 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_rate 0.954478 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_misses 23022 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_mshr_miss_latency 258993499 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_rate 0.954478 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_misses 23022 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_uncacheable 5232 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 155064988 # number of WriteResp MSHR uncacheable cycles
-system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1188.349008 # average number of cycles each access was blocked
+system.cpu4.num_reads 99375 # number of read accesses completed
+system.cpu4.num_writes 53856 # number of write accesses completed
+system.cpu5.l1c.ReadReq_accesses 44846 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_avg_miss_latency 22795.859807 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 22787.860584 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_hits 7526 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_miss_latency 850741488 # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_rate 0.832181 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_misses 37320 # number of ReadReq misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency 850442957 # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832181 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_misses 37320 # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 518680326 # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_accesses 24378 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_avg_miss_latency 24686.676265 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 24679.493004 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_hits 936 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_miss_latency 578705065 # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_rate 0.961605 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_misses 23442 # number of WriteReq misses
+system.cpu5.l1c.WriteReq_mshr_miss_latency 578536675 # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961605 # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_misses 23442 # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 315478251 # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.avg_blocked_cycles_no_mshrs 2288.071694 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu5.l1c.avg_refs 0.414917 # Average number of references to valid blocks.
-system.cpu5.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked
+system.cpu5.l1c.avg_refs 0.412333 # Average number of references to valid blocks.
+system.cpu5.l1c.blocked_no_mshrs 69434 # number of cycles access was blocked
system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles_no_mshrs 82634225 # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_mshrs 158869970 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.demand_accesses 69195 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_avg_miss_latency 13506.011883 # average overall miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency
-system.cpu5.l1c.demand_hits 8686 # number of demand (read+write) hits
-system.cpu5.l1c.demand_miss_latency 817235273 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_rate 0.874471 # miss rate for demand accesses
-system.cpu5.l1c.demand_misses 60509 # number of demand (read+write) misses
+system.cpu5.l1c.demand_accesses 69224 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_avg_miss_latency 23525.337431 # average overall miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 23517.653007 # average overall mshr miss latency
+system.cpu5.l1c.demand_hits 8462 # number of demand (read+write) hits
+system.cpu5.l1c.demand_miss_latency 1429446553 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_rate 0.877759 # miss rate for demand accesses
+system.cpu5.l1c.demand_misses 60762 # number of demand (read+write) misses
system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu5.l1c.demand_mshr_miss_latency 745356829 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_rate 0.874471 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_misses 60509 # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_miss_latency 1428979632 # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_rate 0.877759 # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_misses 60762 # number of demand (read+write) MSHR misses
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.l1c.overall_accesses 69195 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_avg_miss_latency 13506.011883 # average overall miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_hits 8686 # number of overall hits
-system.cpu5.l1c.overall_miss_latency 817235273 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_rate 0.874471 # miss rate for overall accesses
-system.cpu5.l1c.overall_misses 60509 # number of overall misses
+system.cpu5.l1c.overall_accesses 69224 # number of overall (read+write) accesses
+system.cpu5.l1c.overall_avg_miss_latency 23525.337431 # average overall miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 23517.653007 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_hits 8462 # number of overall hits
+system.cpu5.l1c.overall_miss_latency 1429446553 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_rate 0.877759 # miss rate for overall accesses
+system.cpu5.l1c.overall_misses 60762 # number of overall misses
system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu5.l1c.overall_mshr_miss_latency 745356829 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_rate 0.874471 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_misses 60509 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_misses 15001 # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_miss_latency 1428979632 # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_rate 0.877759 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_misses 60762 # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_latency 834158577 # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu5.l1c.protocol.read_invalid 1718821 # read misses to invalid blocks
-system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu5.l1c.protocol.snoop_read_exclusive 2926 # read snoops on exclusive blocks
-system.cpu5.l1c.protocol.snoop_read_modified 12465 # read snoops on modified blocks
-system.cpu5.l1c.protocol.snoop_read_owned 7201 # read snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_read_shared 1810557 # read snoops on shared blocks
-system.cpu5.l1c.protocol.snoop_readex_exclusive 1622 # readEx snoops on exclusive blocks
-system.cpu5.l1c.protocol.snoop_readex_modified 6690 # readEx snoops on modified blocks
-system.cpu5.l1c.protocol.snoop_readex_owned 3947 # readEx snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_readex_shared 12574 # readEx snoops on shared blocks
-system.cpu5.l1c.protocol.snoop_upgrade_owned 818 # upgrade snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_upgrade_shared 3092 # upgradee snoops on shared blocks
-system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu5.l1c.protocol.write_invalid 914561 # write misses to invalid blocks
-system.cpu5.l1c.protocol.write_owned 1422 # write misses to owned blocks
-system.cpu5.l1c.protocol.write_shared 4534 # write misses to shared blocks
-system.cpu5.l1c.replacements 27551 # number of replacements
-system.cpu5.l1c.sampled_refs 27914 # Sample count of references to valid blocks.
+system.cpu5.l1c.replacements 27718 # number of replacements
+system.cpu5.l1c.sampled_refs 28055 # Sample count of references to valid blocks.
system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu5.l1c.tagsinuse 344.440637 # Cycle average of tags in use
-system.cpu5.l1c.total_refs 11582 # Total number of references to valid blocks.
+system.cpu5.l1c.tagsinuse 345.552063 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 11568 # Total number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.writebacks 10931 # number of writebacks
+system.cpu5.l1c.writebacks 10910 # number of writebacks
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 99674 # number of read accesses completed
-system.cpu5.num_writes 53393 # number of write accesses completed
-system.cpu6.l1c.ReadReq_accesses 44595 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_avg_miss_latency 14001.082353 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 12995.526917 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_hits 7462 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_miss_latency 519902191 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_rate 0.832672 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_misses 37133 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency 482562901 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832672 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_misses 37133 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 251671127 # number of ReadResp MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_accesses 24364 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_avg_miss_latency 12854.640783 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 11385.598176 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_hits 1222 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_miss_latency 297482097 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_rate 0.949844 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_misses 23142 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_mshr_miss_latency 263485513 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_rate 0.949844 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_uncacheable 5447 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 163399316 # number of WriteResp MSHR uncacheable cycles
-system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1189.328084 # average number of cycles each access was blocked
+system.cpu5.num_reads 99402 # number of read accesses completed
+system.cpu5.num_writes 54123 # number of write accesses completed
+system.cpu6.l1c.ReadReq_accesses 45284 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_avg_miss_latency 22614.833240 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 22606.834542 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_hits 7625 # number of ReadReq hits
+system.cpu6.l1c.ReadReq_miss_latency 851652005 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_rate 0.831618 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_misses 37659 # number of ReadReq misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency 851350782 # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831618 # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_misses 37659 # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 513879090 # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_accesses 24033 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_avg_miss_latency 25148.091805 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 25140.890430 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_hits 897 # number of WriteReq hits
+system.cpu6.l1c.WriteReq_miss_latency 581826252 # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_rate 0.962676 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_misses 23136 # number of WriteReq misses
+system.cpu6.l1c.WriteReq_mshr_miss_latency 581659641 # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962676 # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_misses 23136 # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 312525316 # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.avg_blocked_cycles_no_mshrs 2288.777328 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu6.l1c.avg_refs 0.411043 # Average number of references to valid blocks.
-system.cpu6.l1c.blocked_no_mshrs 69345 # number of cycles access was blocked
+system.cpu6.l1c.avg_refs 0.407927 # Average number of references to valid blocks.
+system.cpu6.l1c.blocked_no_mshrs 69380 # number of cycles access was blocked
system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles_no_mshrs 82473956 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_mshrs 158795371 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.demand_accesses 68959 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_avg_miss_latency 13560.917263 # average overall miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency
-system.cpu6.l1c.demand_hits 8684 # number of demand (read+write) hits
-system.cpu6.l1c.demand_miss_latency 817384288 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_rate 0.874070 # miss rate for demand accesses
-system.cpu6.l1c.demand_misses 60275 # number of demand (read+write) misses
+system.cpu6.l1c.demand_accesses 69317 # number of demand (read+write) accesses
+system.cpu6.l1c.demand_avg_miss_latency 23578.884069 # average overall miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 23571.188798 # average overall mshr miss latency
+system.cpu6.l1c.demand_hits 8522 # number of demand (read+write) hits
+system.cpu6.l1c.demand_miss_latency 1433478257 # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_rate 0.877058 # miss rate for demand accesses
+system.cpu6.l1c.demand_misses 60795 # number of demand (read+write) misses
system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu6.l1c.demand_mshr_miss_latency 746048414 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_rate 0.874070 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_misses 60275 # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_miss_latency 1433010423 # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_rate 0.877058 # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_misses 60795 # number of demand (read+write) MSHR misses
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.l1c.overall_accesses 68959 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_avg_miss_latency 13560.917263 # average overall miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_hits 8684 # number of overall hits
-system.cpu6.l1c.overall_miss_latency 817384288 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_rate 0.874070 # miss rate for overall accesses
-system.cpu6.l1c.overall_misses 60275 # number of overall misses
+system.cpu6.l1c.overall_accesses 69317 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_avg_miss_latency 23578.884069 # average overall miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 23571.188798 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_hits 8522 # number of overall hits
+system.cpu6.l1c.overall_miss_latency 1433478257 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_rate 0.877058 # miss rate for overall accesses
+system.cpu6.l1c.overall_misses 60795 # number of overall misses
system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu6.l1c.overall_mshr_miss_latency 746048414 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_rate 0.874070 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_misses 60275 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_misses 15267 # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_miss_latency 1433010423 # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_rate 0.877058 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_misses 60795 # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_latency 826404406 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu6.l1c.protocol.read_invalid 1894590 # read misses to invalid blocks
-system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu6.l1c.protocol.snoop_read_exclusive 2887 # read snoops on exclusive blocks
-system.cpu6.l1c.protocol.snoop_read_modified 12551 # read snoops on modified blocks
-system.cpu6.l1c.protocol.snoop_read_owned 7188 # read snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_read_shared 1703425 # read snoops on shared blocks
-system.cpu6.l1c.protocol.snoop_readex_exclusive 1550 # readEx snoops on exclusive blocks
-system.cpu6.l1c.protocol.snoop_readex_modified 6733 # readEx snoops on modified blocks
-system.cpu6.l1c.protocol.snoop_readex_owned 3926 # readEx snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_readex_shared 12456 # readEx snoops on shared blocks
-system.cpu6.l1c.protocol.snoop_upgrade_owned 800 # upgrade snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_upgrade_shared 3156 # upgradee snoops on shared blocks
-system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu6.l1c.protocol.write_invalid 987928 # write misses to invalid blocks
-system.cpu6.l1c.protocol.write_owned 1405 # write misses to owned blocks
-system.cpu6.l1c.protocol.write_shared 4406 # write misses to shared blocks
-system.cpu6.l1c.replacements 27613 # number of replacements
-system.cpu6.l1c.sampled_refs 27946 # Sample count of references to valid blocks.
+system.cpu6.l1c.replacements 27931 # number of replacements
+system.cpu6.l1c.sampled_refs 28282 # Sample count of references to valid blocks.
system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu6.l1c.tagsinuse 344.860122 # Cycle average of tags in use
-system.cpu6.l1c.total_refs 11487 # Total number of references to valid blocks.
+system.cpu6.l1c.tagsinuse 346.778818 # Cycle average of tags in use
+system.cpu6.l1c.total_refs 11537 # Total number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.writebacks 11073 # number of writebacks
+system.cpu6.l1c.writebacks 10819 # number of writebacks
system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 98723 # number of read accesses completed
-system.cpu6.num_writes 53876 # number of write accesses completed
-system.cpu7.l1c.ReadReq_accesses 44990 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_avg_miss_latency 13952.283047 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 12937.789329 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_hits 7505 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_miss_latency 523001330 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_rate 0.833185 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_misses 37485 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency 484973033 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833185 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_misses 37485 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable 10001 # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 257188342 # number of ReadResp MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_accesses 24083 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_avg_miss_latency 12615.682417 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 11155.458639 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_hits 1163 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_miss_latency 289151441 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_rate 0.951709 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_misses 22920 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_mshr_miss_latency 255683112 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_rate 0.951709 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_misses 22920 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_uncacheable 5323 # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 159397105 # number of WriteResp MSHR uncacheable cycles
-system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1185.864523 # average number of cycles each access was blocked
+system.cpu6.num_reads 100000 # number of read accesses completed
+system.cpu6.num_writes 53600 # number of write accesses completed
+system.cpu7.l1c.ReadReq_accesses 44617 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_avg_miss_latency 22791.302160 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 22783.302456 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_hits 7491 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_miss_latency 846149884 # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_rate 0.832104 # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_misses 37126 # number of ReadReq misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency 845852887 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate 0.832104 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_misses 37126 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 523016698 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_accesses 24432 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_avg_miss_latency 24654.748978 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 24647.585464 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_hits 960 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_miss_latency 578696268 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_rate 0.960707 # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_misses 23472 # number of WriteReq misses
+system.cpu7.l1c.WriteReq_mshr_miss_latency 578528126 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_rate 0.960707 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_misses 23472 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 310262407 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.avg_blocked_cycles_no_mshrs 2294.299163 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu7.l1c.avg_refs 0.413879 # Average number of references to valid blocks.
-system.cpu7.l1c.blocked_no_mshrs 69665 # number of cycles access was blocked
+system.cpu7.l1c.avg_refs 0.417293 # Average number of references to valid blocks.
+system.cpu7.l1c.blocked_no_mshrs 69407 # number of cycles access was blocked
system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles_no_mshrs 82613252 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_mshrs 159240422 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.demand_accesses 69073 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_avg_miss_latency 13445.124923 # average overall miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency
-system.cpu7.l1c.demand_hits 8668 # number of demand (read+write) hits
-system.cpu7.l1c.demand_miss_latency 812152771 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_rate 0.874510 # miss rate for demand accesses
-system.cpu7.l1c.demand_misses 60405 # number of demand (read+write) misses
+system.cpu7.l1c.demand_accesses 69049 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_avg_miss_latency 23513.088749 # average overall miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 23505.412934 # average overall mshr miss latency
+system.cpu7.l1c.demand_hits 8451 # number of demand (read+write) hits
+system.cpu7.l1c.demand_miss_latency 1424846152 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_rate 0.877609 # miss rate for demand accesses
+system.cpu7.l1c.demand_misses 60598 # number of demand (read+write) misses
system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu7.l1c.demand_mshr_miss_latency 740656145 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_rate 0.874510 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_misses 60405 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_miss_latency 1424381013 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_rate 0.877609 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_misses 60598 # number of demand (read+write) MSHR misses
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.l1c.overall_accesses 69073 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_avg_miss_latency 13445.124923 # average overall miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_hits 8668 # number of overall hits
-system.cpu7.l1c.overall_miss_latency 812152771 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_rate 0.874510 # miss rate for overall accesses
-system.cpu7.l1c.overall_misses 60405 # number of overall misses
+system.cpu7.l1c.overall_accesses 69049 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_avg_miss_latency 23513.088749 # average overall miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 23505.412934 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_hits 8451 # number of overall hits
+system.cpu7.l1c.overall_miss_latency 1424846152 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_rate 0.877609 # miss rate for overall accesses
+system.cpu7.l1c.overall_misses 60598 # number of overall misses
system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu7.l1c.overall_mshr_miss_latency 740656145 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_rate 0.874510 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_misses 60405 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_misses 15324 # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_miss_latency 1424381013 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_rate 0.877609 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_misses 60598 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_latency 833279105 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu7.l1c.protocol.read_invalid 1929884 # read misses to invalid blocks
-system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
-system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
-system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
-system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu7.l1c.protocol.snoop_read_exclusive 2904 # read snoops on exclusive blocks
-system.cpu7.l1c.protocol.snoop_read_modified 12387 # read snoops on modified blocks
-system.cpu7.l1c.protocol.snoop_read_owned 7174 # read snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_read_shared 1782059 # read snoops on shared blocks
-system.cpu7.l1c.protocol.snoop_readex_exclusive 1587 # readEx snoops on exclusive blocks
-system.cpu7.l1c.protocol.snoop_readex_modified 6687 # readEx snoops on modified blocks
-system.cpu7.l1c.protocol.snoop_readex_owned 3842 # readEx snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_readex_shared 12759 # readEx snoops on shared blocks
-system.cpu7.l1c.protocol.snoop_upgrade_owned 792 # upgrade snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_upgrade_shared 3085 # upgradee snoops on shared blocks
-system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
-system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
-system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
-system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
-system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu7.l1c.protocol.write_invalid 930930 # write misses to invalid blocks
-system.cpu7.l1c.protocol.write_owned 1422 # write misses to owned blocks
-system.cpu7.l1c.protocol.write_shared 4465 # write misses to shared blocks
-system.cpu7.l1c.replacements 27486 # number of replacements
-system.cpu7.l1c.sampled_refs 27827 # Sample count of references to valid blocks.
+system.cpu7.l1c.replacements 27613 # number of replacements
+system.cpu7.l1c.sampled_refs 27942 # Sample count of references to valid blocks.
system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu7.l1c.tagsinuse 344.310963 # Cycle average of tags in use
-system.cpu7.l1c.total_refs 11517 # Total number of references to valid blocks.
+system.cpu7.l1c.tagsinuse 345.414592 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 11660 # Total number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.writebacks 10979 # number of writebacks
+system.cpu7.l1c.writebacks 10955 # number of writebacks
system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 99734 # number of read accesses completed
-system.cpu7.num_writes 53652 # number of write accesses completed
-system.l2c.ReadExReq_accesses 75160 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 10115.633652 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 6085.503709 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits 39620 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 359509620 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 0.472858 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 35540 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_hits 220 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_miss_latency 214939991 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 0.469931 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 35320 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 138762 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 10150.344064 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 6129.500996 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits 72597 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 671597515 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.476824 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 66165 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 403069856 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.473898 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 65759 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable 78927 # number of ReadReq MSHR uncacheable
-system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.l2c.ReadResp_mshr_uncacheable_latency 484683934 # number of ReadResp MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable 42802 # number of WriteReq MSHR uncacheable
-system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.l2c.WriteResp_mshr_uncacheable_latency 248118294 # number of WriteResp MSHR uncacheable cycles
-system.l2c.Writeback_accesses 86706 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 18948 # number of Writeback hits
-system.l2c.Writeback_miss_rate 0.781468 # miss rate for Writeback accesses
-system.l2c.Writeback_misses 67758 # number of Writeback misses
-system.l2c.Writeback_mshr_miss_rate 0.781468 # mshr miss rate for Writeback accesses
-system.l2c.Writeback_mshr_misses 67758 # number of Writeback MSHR misses
+system.cpu7.num_reads 98933 # number of read accesses completed
+system.cpu7.num_writes 53679 # number of write accesses completed
+system.l2c.ReadExReq_accesses 74732 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 10058.723893 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 10012.709549 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 751708554 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 74732 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_hits 486 # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_miss_latency 748269810 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 74732 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 138119 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 10093.112454 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 10012.902949 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 62746 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 760748165 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.545711 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 75373 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 858 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 754702534 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.545711 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 75373 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 792432163 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 18312 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 5090.815258 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 10012.622433 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 93223009 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 18312 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_hits 25 # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_miss_latency 183351142 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 18312 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 430029394 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 86893 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.l2c.Writeback_misses 86893 # number of Writeback misses
+system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.l2c.Writeback_mshr_misses 86893 # number of Writeback MSHR misses
system.l2c.avg_blocked_cycles_no_mshrs 3278 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.297661 # Average number of references to valid blocks.
+system.l2c.avg_refs 3.318198 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 3 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 9834 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 138762 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 10150.344064 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency
-system.l2c.demand_hits 72597 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 671597515 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.476824 # miss rate for demand accesses
-system.l2c.demand_misses 66165 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 406 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 403069856 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.473898 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 65759 # number of demand (read+write) MSHR misses
+system.l2c.demand_accesses 212851 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 10075.991599 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 10012.806662 # average overall mshr miss latency
+system.l2c.demand_hits 62746 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 1512456719 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.705212 # miss rate for demand accesses
+system.l2c.demand_misses 150105 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 1344 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 1502972344 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.705212 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 150105 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 225468 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 5014.803394 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.l2c.overall_hits 91545 # number of overall hits
-system.l2c.overall_miss_latency 671597515 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.593978 # miss rate for overall accesses
-system.l2c.overall_misses 133923 # number of overall misses
-system.l2c.overall_mshr_hits 406 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 403069856 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.291656 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 65759 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 121729 # number of overall MSHR uncacheable misses
+system.l2c.overall_accesses 212851 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 10075.991599 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 10012.806662 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 62746 # number of overall hits
+system.l2c.overall_miss_latency 1512456719 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.705212 # miss rate for overall accesses
+system.l2c.overall_misses 150105 # number of overall misses
+system.l2c.overall_mshr_hits 1344 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 1502972344 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.705212 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 150105 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1222461557 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 100054 # number of replacements
-system.l2c.sampled_refs 101078 # Sample count of references to valid blocks.
+system.l2c.replacements 31000 # number of replacements
+system.l2c.sampled_refs 31427 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1023.099242 # Cycle average of tags in use
-system.l2c.total_refs 131165 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 296156 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 16243 # number of writebacks
+system.l2c.tagsinuse 461.978673 # Cycle average of tags in use
+system.l2c.total_refs 104281 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 0 # number of writebacks
---------- End Simulation Statistics ----------
warn: Entering event queue @ 0. Starting simulation...
-system.cpu7: completed 10000 read accesses @8253930
-system.cpu1: completed 10000 read accesses @8325085
-system.cpu6: completed 10000 read accesses @8427313
-system.cpu4: completed 10000 read accesses @8438233
-system.cpu2: completed 10000 read accesses @8458126
-system.cpu5: completed 10000 read accesses @8549800
-system.cpu3: completed 10000 read accesses @8559995
-system.cpu0: completed 10000 read accesses @8593654
-system.cpu7: completed 20000 read accesses @16744182
-system.cpu1: completed 20000 read accesses @16774744
-system.cpu4: completed 20000 read accesses @16786220
-system.cpu3: completed 20000 read accesses @16787358
-system.cpu5: completed 20000 read accesses @16795808
-system.cpu6: completed 20000 read accesses @16836913
-system.cpu2: completed 20000 read accesses @17031052
-system.cpu0: completed 20000 read accesses @17126654
-system.cpu5: completed 30000 read accesses @24892576
-system.cpu6: completed 30000 read accesses @24903300
-system.cpu3: completed 30000 read accesses @24935860
-system.cpu4: completed 30000 read accesses @25020642
-system.cpu1: completed 30000 read accesses @25031726
-system.cpu7: completed 30000 read accesses @25112091
-system.cpu2: completed 30000 read accesses @25235960
-system.cpu0: completed 30000 read accesses @25505209
-system.cpu5: completed 40000 read accesses @33191203
-system.cpu6: completed 40000 read accesses @33273684
-system.cpu4: completed 40000 read accesses @33345526
-system.cpu3: completed 40000 read accesses @33406412
-system.cpu7: completed 40000 read accesses @33509130
-system.cpu1: completed 40000 read accesses @33509218
-system.cpu2: completed 40000 read accesses @33664822
-system.cpu0: completed 40000 read accesses @33869626
-system.cpu5: completed 50000 read accesses @41488848
-system.cpu4: completed 50000 read accesses @41582702
-system.cpu7: completed 50000 read accesses @41828988
-system.cpu3: completed 50000 read accesses @41829496
-system.cpu1: completed 50000 read accesses @41849534
-system.cpu6: completed 50000 read accesses @41982608
-system.cpu2: completed 50000 read accesses @42197798
-system.cpu0: completed 50000 read accesses @42443468
-system.cpu5: completed 60000 read accesses @49751344
-system.cpu4: completed 60000 read accesses @49783100
-system.cpu1: completed 60000 read accesses @49918062
-system.cpu7: completed 60000 read accesses @49929008
-system.cpu3: completed 60000 read accesses @50173996
-system.cpu6: completed 60000 read accesses @50351766
-system.cpu2: completed 60000 read accesses @50352657
-system.cpu0: completed 60000 read accesses @50789771
-system.cpu4: completed 70000 read accesses @58352386
-system.cpu5: completed 70000 read accesses @58394758
-system.cpu7: completed 70000 read accesses @58570698
-system.cpu1: completed 70000 read accesses @58764169
-system.cpu3: completed 70000 read accesses @58764648
-system.cpu2: completed 70000 read accesses @58921714
-system.cpu6: completed 70000 read accesses @58929984
-system.cpu0: completed 70000 read accesses @59567320
-system.cpu1: completed 80000 read accesses @67092786
-system.cpu5: completed 80000 read accesses @67153667
-system.cpu4: completed 80000 read accesses @67153760
-system.cpu7: completed 80000 read accesses @67207042
-system.cpu3: completed 80000 read accesses @67238507
-system.cpu2: completed 80000 read accesses @67633112
-system.cpu6: completed 80000 read accesses @67664637
-system.cpu0: completed 80000 read accesses @68437288
-system.cpu1: completed 90000 read accesses @75679048
-system.cpu4: completed 90000 read accesses @75680280
-system.cpu7: completed 90000 read accesses @75751053
-system.cpu5: completed 90000 read accesses @75781514
-system.cpu3: completed 90000 read accesses @75844118
-system.cpu2: completed 90000 read accesses @76346671
-system.cpu6: completed 90000 read accesses @76491728
-system.cpu0: completed 90000 read accesses @77376872
-system.cpu1: completed 100000 read accesses @84350509
+system.cpu7: completed 10000 read accesses @15607088
+system.cpu1: completed 10000 read accesses @15686239
+system.cpu5: completed 10000 read accesses @15771479
+system.cpu4: completed 10000 read accesses @15772513
+system.cpu0: completed 10000 read accesses @15778178
+system.cpu6: completed 10000 read accesses @15791633
+system.cpu2: completed 10000 read accesses @15841990
+system.cpu3: completed 10000 read accesses @15878600
+system.cpu2: completed 20000 read accesses @31878727
+system.cpu7: completed 20000 read accesses @32026154
+system.cpu6: completed 20000 read accesses @32057190
+system.cpu1: completed 20000 read accesses @32240417
+system.cpu0: completed 20000 read accesses @32270672
+system.cpu3: completed 20000 read accesses @32335938
+system.cpu5: completed 20000 read accesses @32480722
+system.cpu4: completed 20000 read accesses @32490454
+system.cpu2: completed 30000 read accesses @48060100
+system.cpu6: completed 30000 read accesses @48167196
+system.cpu4: completed 30000 read accesses @48520588
+system.cpu7: completed 30000 read accesses @48646309
+system.cpu0: completed 30000 read accesses @48740616
+system.cpu1: completed 30000 read accesses @48766857
+system.cpu3: completed 30000 read accesses @48959010
+system.cpu5: completed 30000 read accesses @49028132
+system.cpu6: completed 40000 read accesses @64421948
+system.cpu4: completed 40000 read accesses @64637670
+system.cpu2: completed 40000 read accesses @64868400
+system.cpu1: completed 40000 read accesses @64925788
+system.cpu0: completed 40000 read accesses @64956331
+system.cpu3: completed 40000 read accesses @65406565
+system.cpu5: completed 40000 read accesses @65517578
+system.cpu7: completed 40000 read accesses @65556693
+system.cpu6: completed 50000 read accesses @80917227
+system.cpu2: completed 50000 read accesses @80917444
+system.cpu4: completed 50000 read accesses @81159816
+system.cpu1: completed 50000 read accesses @81373401
+system.cpu3: completed 50000 read accesses @81540449
+system.cpu0: completed 50000 read accesses @81577912
+system.cpu5: completed 50000 read accesses @81975441
+system.cpu7: completed 50000 read accesses @82285501
+system.cpu2: completed 60000 read accesses @96985412
+system.cpu4: completed 60000 read accesses @97174738
+system.cpu6: completed 60000 read accesses @97530786
+system.cpu0: completed 60000 read accesses @97671589
+system.cpu3: completed 60000 read accesses @97821937
+system.cpu1: completed 60000 read accesses @97822818
+system.cpu5: completed 60000 read accesses @98044596
+system.cpu7: completed 60000 read accesses @98812006
+system.cpu2: completed 70000 read accesses @113400661
+system.cpu4: completed 70000 read accesses @113949415
+system.cpu1: completed 70000 read accesses @114120869
+system.cpu3: completed 70000 read accesses @114207385
+system.cpu0: completed 70000 read accesses @114307850
+system.cpu6: completed 70000 read accesses @114393410
+system.cpu5: completed 70000 read accesses @114714609
+system.cpu7: completed 70000 read accesses @115286783
+system.cpu2: completed 80000 read accesses @130149084
+system.cpu0: completed 80000 read accesses @130494872
+system.cpu4: completed 80000 read accesses @130604588
+system.cpu6: completed 80000 read accesses @130741327
+system.cpu1: completed 80000 read accesses @130791488
+system.cpu3: completed 80000 read accesses @130805400
+system.cpu5: completed 80000 read accesses @130975948
+system.cpu7: completed 80000 read accesses @131555733
+system.cpu2: completed 90000 read accesses @146468442
+system.cpu6: completed 90000 read accesses @146616353
+system.cpu1: completed 90000 read accesses @146926939
+system.cpu3: completed 90000 read accesses @147059543
+system.cpu0: completed 90000 read accesses @147067458
+system.cpu5: completed 90000 read accesses @147440946
+system.cpu4: completed 90000 read accesses @147560717
+system.cpu7: completed 90000 read accesses @148115904
+system.cpu6: completed 100000 read accesses @163182312
All Rights Reserved
-M5 compiled Jun 10 2007 14:06:20
-M5 started Sun Jun 10 14:22:51 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
+M5 compiled Aug 3 2007 03:56:47
+M5 started Fri Aug 3 04:17:16 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 84350509 because Maximum number of loads reached!
+Exiting @ tick 163182312 because maximum number of loads reached
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=drivesys.physmem
-readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS
+readfile=/z/stever/hg/m5.stever/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
[drivesys.cpu]
type=AtomicSimpleCPU
-children=dtb itb
+children=dtb itb tracer
clock=1
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=drivesys
+tracer=drivesys.cpu.tracer
width=1
dcache_port=drivesys.membus.port[3]
icache_port=drivesys.membus.port[2]
type=AlphaITB
size=48
+[drivesys.cpu.tracer]
+type=ExeTracer
+
[drivesys.disk0]
type=IdeDisk
children=image
pio_latency=1000
platform=drivesys.tsunami
system=drivesys
-time=2009 1 1 0 0 0 3 1
+time=Thu Jan 1 00:00:00 2009
tsunami=drivesys.tsunami
year_is_bcd=false
pio=drivesys.iobus.port[23]
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=testsys.physmem
-readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS
+readfile=/z/stever/hg/m5.stever/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
[testsys.cpu]
type=AtomicSimpleCPU
-children=dtb itb
+children=dtb itb tracer
clock=1
cpu_id=0
defer_registration=false
progress_interval=0
simulate_stalls=false
system=testsys
+tracer=testsys.cpu.tracer
width=1
dcache_port=testsys.membus.port[3]
icache_port=testsys.membus.port[2]
type=AlphaITB
size=48
+[testsys.cpu.tracer]
+type=ExeTracer
+
[testsys.disk0]
type=IdeDisk
children=image
pio_latency=1000
platform=testsys.tsunami
system=testsys
-time=2009 1 1 0 0 0 3 1
+time=Thu Jan 1 00:00:00 2009
tsunami=testsys.tsunami
year_is_bcd=false
pio=testsys.iobus.port[23]
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-host_inst_rate 6618724 # Simulator instruction rate (inst/s)
-host_seconds 41.30 # Real time elapsed on the host
-host_tick_rate 4842704130 # Simulator tick rate (ticks/s)
+host_inst_rate 51081325 # Simulator instruction rate (inst/s)
+host_mem_usage 406704 # Number of bytes of host memory used
+host_seconds 5.35 # Real time elapsed on the host
+host_tick_rate 37372483621 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-host_inst_rate 65191624612 # Simulator instruction rate (inst/s)
+host_inst_rate 71036507796 # Simulator instruction rate (inst/s)
+host_mem_usage 406704 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
-host_tick_rate 183725573 # Simulator tick rate (ticks/s)
+host_tick_rate 191282064 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
-Listening for testsys connection on port 3456
-Listening for drivesys connection on port 3457
-0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000
-0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001
+Listening for testsys connection on port 3457
+Listening for drivesys connection on port 3458
+0: testsys.remote_gdb.listener: listening for remote gdb on port 7001
+0: drivesys.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: Obsolete M5 instruction ivlb encountered.
All Rights Reserved
-M5 compiled Jun 10 2007 14:10:03
-M5 started Mon Jun 11 01:47:32 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+M5 compiled Aug 3 2007 04:02:11
+M5 started Fri Aug 3 04:26:58 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
- 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
- 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 4300235844056 because checkpoint
projects / gem5.git / commitdiff