i965: Disable register spilling on gen6 until it's fixed.

Avoids GPU hang on glsl-fs-convolution-1.

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index d7acc30fc464947bd2029d89e1c03c59928d45c2..bbb210cd449bdc71b4ff521dd63644e499a3b5b8 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -225,7 +225,7 @@ fs_visitor::assign_regs()
        * loop back into here to try again.
        */
       int reg = choose_spill_reg(g);
-      if (reg == -1) {
+      if (reg == -1 || intel->gen >= 6) {
         this->fail = true;
       } else {
         spill_reg(reg);