Factor out SPI flash resource definition.

diff --git a/nmigen_boards/dev/__init__.py b/nmigen_boards/dev/__init__.py
new file mode 100644 (file)
index 0000000..b27acfa
--- /dev/null
+++ b/nmigen_boards/dev/__init__.py
@@ -0,0 +1 @@
+from .flash import SPIFlashResources

diff --git a/nmigen_boards/dev/flash.py b/nmigen_boards/dev/flash.py
new file mode 100644 (file)
index 0000000..a4b5e33
--- /dev/null
+++ b/nmigen_boards/dev/flash.py
@@ -0,0 +1,36 @@
+from nmigen.build import *
+
+
+__all__ = ["SPIFlashResources"]
+
+
+def SPIFlashResources(number, *, cs_n, clk, mosi, miso, wp_n=None, hold_n=None, attrs=None):
+    resources = []
+
+    io_all = []
+    if attrs is not None:
+        io_all.append(attrs)
+    io_all.append(Subsignal("cs_n", Pins(cs_n, dir="o")))
+    io_all.append(Subsignal("clk",  Pins(clk,  dir="o")))
+
+    io_1x = list(io_all)
+    io_1x.append(Subsignal("mosi", Pins(mosi, dir="o")))
+    io_1x.append(Subsignal("miso", Pins(miso, dir="i")))
+    if wp_n is not None and hold_n is not None:
+        # Tristate these pins by default, and rely on a pullup on the board or within the flash.
+        # An alternative would be to define them as outputs with reset value of 1, but that's
+        # not currently possible in nMigen.
+        io_1x.append(Subsignal("wp_n",   Pins(wp_n, dir="oe")))
+        io_1x.append(Subsignal("hold_n", Pins(hold_n, dir="oe")))
+    resources.append(Resource("spiflash", number, *io_1x))
+
+    io_2x = list(io_all)
+    io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io")))
+    resources.append(Resource("spiflash2x", number, *io_2x))
+
+    if wp_n is not None and hold_n is not None:
+        io_4x = list(io_all)
+        io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp_n, hold_n]), dir="io")))
+        resources.append(Resource("spiflash4x", number, *io_4x))
+
+    return resources

diff --git a/nmigen_boards/ice40_hx1k_blink_evn.py b/nmigen_boards/ice40_hx1k_blink_evn.py
index 1acac2d64fd607c105b46a66e2e672c1bf64a524..11b454e7fc0aa5ae0b27ce4f3421fb7eeb17072d 100644 (file)
--- a/nmigen_boards/ice40_hx1k_blink_evn.py
+++ b/nmigen_boards/ice40_hx1k_blink_evn.py
@@ -3,6 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
+from .dev import *
 
 
 __all__ = ["ICE40HX1KBlinkEVNPlatform"]
@@ -25,12 +26,10 @@ class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
         Resource("user_btn", 2, Pins("54"), Attrs(IO_STANDARD="SB_LVCMOS33")),
         Resource("user_btn", 3, Pins("52"), Attrs(IO_STANDARD="SB_LVCMOS33")),
 
-        Resource("spiflash", 0,
-            Subsignal("cs_n", Pins("49", dir="o")),
-            Subsignal("clk",  Pins("48", dir="o")),
-            Subsignal("mosi", Pins("45", dir="o")),
-            Subsignal("miso", Pins("46", dir="i")),
-            Attrs(IO_STANDARD="SB_LVCMOS33")
+        *SPIFlashResources(0,
+            cs_n="49", clk="48",
+            mosi="45", miso="46",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
         ),
     ]
     connectors = [

diff --git a/nmigen_boards/icebreaker.py b/nmigen_boards/icebreaker.py
index 7993adba665205af3aad20ce9fb966e5089adc5b..0b84b5662888b967dc93472a19e737e1874edd38 100644 (file)
--- a/nmigen_boards/icebreaker.py
+++ b/nmigen_boards/icebreaker.py
@@ -3,6 +3,7 @@ import subprocess
 \r
 from nmigen.build import *\r
 from nmigen.vendor.lattice_ice40 import *\r
+from .dev import *\r
 \r
 \r
 __all__ = ["ICEBreakerPlatform"]\r
@@ -28,21 +29,11 @@ class ICEBreakerPlatform(LatticeICE40Platform):
             Attrs(IO_STANDARD="SB_LVTTL")\r
         ),\r
 \r
-        Resource("spiflash", 0,\r
-            Subsignal("cs_n", Pins("16", dir="o")),\r
-            Subsignal("clk",  Pins("15", dir="o")),\r
-            Subsignal("mosi", Pins("14", dir="o")),\r
-            Subsignal("miso", Pins("17", dir="i")),\r
-            Subsignal("wp",   Pins("12", dir="o")),\r
-            Subsignal("hold", Pins("13", dir="o")),\r
-            Attrs(IO_STANDARD="SB_LVCMOS33")\r
-        ),\r
-\r
-        Resource("spiflash4x", 0,\r
-            Subsignal("cs_n", Pins("16", dir="o")),\r
-            Subsignal("clk",  Pins("15", dir="o")),\r
-            Subsignal("dq",   Pins("14 17 12 13", dir="io")),\r
-            Attrs(IO_STANDARD="SB_LVCMOS33")\r
+        *SPIFlashResources(0,\r
+            cs_n="16", clk="15",\r
+            mosi="14", miso="17",\r
+            wp_n="12", hold_n="13",\r
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33")\r
         ),\r
     ]\r
     connectors = [\r

diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py
index a60f8c9315c1b9b13bf9b5c9ce99269e43cbd1aa..cf5c81ce872bcd5ed364a4806af288edc40235a7 100644 (file)
--- a/nmigen_boards/icestick.py
+++ b/nmigen_boards/icestick.py
@@ -3,6 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
+from .dev import *
 
 
 __all__ = ["ICEStickPlatform"]
@@ -39,12 +40,10 @@ class ICEStickPlatform(LatticeICE40Platform):
             Attrs(IO_STANDARD="SB_LVCMOS33")
         ),
 
-        Resource("spiflash", 0,
-            Subsignal("cs_n", Pins("71", dir="o")),
-            Subsignal("clk",  Pins("70", dir="o")),
-            Subsignal("mosi", Pins("67", dir="o")),
-            Subsignal("miso", Pins("68", dir="i")),
-            Attrs(IO_STANDARD="SB_LVCMOS33")
+        *SPIFlashResources(0,
+            cs_n="71", clk="70",
+            mosi="67", miso="68",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
         ),
     ]
     connectors = [

diff --git a/nmigen_boards/tinyfpga_bx.py b/nmigen_boards/tinyfpga_bx.py
index d9b0116ad5bc863cec72a3e27f86596550cb40f9..544e0ce3a9236a937d5f90f823798a056b994d40 100644 (file)
--- a/nmigen_boards/tinyfpga_bx.py
+++ b/nmigen_boards/tinyfpga_bx.py
@@ -3,6 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
+from .dev import *
 
 
 __all__ = ["TinyFPGABXPlatform"]
@@ -24,22 +25,10 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
             Attrs(IO_STANDARD="SB_LVCMOS33")
         ),
 
-        Resource("spiflash", 0,
-            Subsignal("cs_n", Pins("F7", dir="o")),
-            Subsignal("clk",  Pins("G7", dir="o")),
-            Subsignal("mosi", Pins("G6", dir="o")),
-            Subsignal("miso", Pins("H7", dir="i")),
-            Subsignal("wp",   Pins("H4", dir="o")),
-            Subsignal("hold", Pins("J8", dir="o")),
-            Attrs(IO_STANDARD="SB_LVCMOS33")
-        ),
-
-        Resource("spiflash4x", 0,
-            Subsignal("cs_n", Pins("F7", dir="o")),
-            Subsignal("clk",  Pins("G7", dir="o")),
-            Subsignal("dq",   Pins("G6 H7 H4 J8", dir="io")),
-            Attrs(IO_STANDARD="SB_LVCMOS33")
-        ),
+        *SPIFlashResources(0,
+            cs_n="F7", clk="G7",
+            mosi="G6", miso="H7", wp_n="H4", hold_n="J8",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
     ]
     connectors = [
         Connector("gpio", 0,