ecp5: Add DDRDLLA

Signed-off-by: David Shah <davey1576@gmail.com>

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index bac17260f85e8201cd16fc08817404079cc56a08..223e19b9efd08ed140e236ac8651db8db87cdb6b 100644 (file)
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -308,6 +308,15 @@ module DQSBUFM(
        parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module DDRDLLA(
+       input CLK, RST, UDDCNTLN, FREEZE,
+       output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
+);
+       parameter FORCE_MAX_DELAY = "NO";
+       parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module CLKDIVF(
        input CLKI, RST, ALIGNWD,