It is at least as fast as xor on any processor except a Pentium. */
if (operands[1] == const1_rtx
- && ix86_cpu == PROCESSOR_PENTIUM
+ && TARGET_PENTIUM
&& (link = find_reg_note (insn, REG_WAS_0, 0))
/* Make sure the insn that stored the 0 is still present. */
&& ! INSN_DELETED_P (XEXP (link, 0))
/* movb $0,reg8 is 2 bytes, the same as xorl reg8,reg8. */
if (operands[1] == const1_rtx
- && ix86_cpu == PROCESSOR_PENTIUM
+ && TARGET_PENTIUM
&& ! NON_QI_REG_P (operands[0])
&& (link = find_reg_note (insn, REG_WAS_0, 0))
/* Make sure the insn that stored the 0 is still present. */
"operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
(define_insn "zero_extendsidi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?m")
- (zero_extend:DI (match_operand:SI 1 "register_operand" "0,rm,r")))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
+ (zero_extend:DI (match_operand:SI 1 "general_operand" "0,rm,r")))]
""
- "*
- {
- rtx high[2], low[2], xops[4];
-
- if (REG_P (operands[0]) && REG_P (operands[1])
- && REGNO (operands[0]) == REGNO (operands[1]))
- {
- operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- return AS2 (xor%L0,%0,%0);
- }
-
- split_di (operands, 1, low, high);
- xops[0] = low[0];
- xops[1] = operands[1];
- xops[2] = high[0];
- xops[3] = const0_rtx;
-
- output_asm_insn (AS2 (mov%L0,%1,%0), xops);
- if (GET_CODE (low[0]) == MEM)
- output_asm_insn (AS2 (mov%L2,%3,%2), xops);
- else
- output_asm_insn (AS2 (xor%L2,%2,%2), xops);
+ "#")
- RET;
-}")
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
+ "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])"
+ [(set (match_dup 4) (const_int 0))]
+ "split_di (&operands[0], 1, &operands[3], &operands[4]);")
+
+(define_split
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
+ "reload_completed"
+ [(set (match_dup 3) (match_dup 1))
+ (set (match_dup 4) (const_int 0))]
+ "split_di (&operands[0], 1, &operands[3], &operands[4]);")
\f
;;- sign extension instructions
RET;
}")
+(define_insn "ashrsi3_31"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,d")
+ (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,a")
+ (const_int 31)))]
+ "!TARGET_PENTIUM || optimize_size"
+ "@
+ sar%L0 $31,%0
+ cltd")
+
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")